- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67681 > IBM21P100BGB PCI BUS CONTROLLER, PBGA304 PDF資料下載
參數(shù)資料
| 型號： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 61/140頁 |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當(dāng)前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_operations.fm.03
July 9, 2001
Bus Operation
Page 19 of 131
3.3.3.2 Type 0 Configuration Read
The Type 0 Configuration Read command is only accepted on the primary interface. The command returns
immediate data regardless of interface mode.
3.3.4 Non-Prefetchable and DWord Reads
A non-prefetchable read transaction is a read transaction in which the bridge requests exactly one DWord
from the target and disconnects the initiator after delivering that one DWord of read data. Unlike prefetchable
read transactions, the bridge forwards the read byte enable information for the data phase.
Non-prefetchable behavior is used for I/O, configuration, memory read transactions that fall into the non-
prefetchable memory space for PCI mode, and all DWord read transactions in PCI-X mode.
3.3.5 Prefetchable Reads
A prefetchable read transaction is a read transaction where the bridge performs speculative reads, transfer-
ring data from the target before it is requested from the initiator. This behavior allows a prefetchable read
transaction to consist of multiple data transfers. For prefetchable read transactions, all byte enables are
asserted for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for
memory read transactions that fall into prefetchable memory space and are allowed to fetch more than a
DWord. The amount of data that is prefetched depends on the type of transaction and the setting of bits in the
Primary and Secondary Data Buffering Control registers in configuration space. The amount of prefetching
may also be affected by the amount of free buffer space available in the bridge, and by any read address
boundaries encountered (cache line for cache line reads and 1M address boundary to ensure that a read
does not cross into other devices’ space).
3.3.5.1 Algorithm for PCI-to-PCI Mode
The algorithm used for transfers in PCI-to-PCI mode is user defined in the Primary and Secondary Data Buff-
ering Control registers. These registers have bits for memory read to prefetchable space, memory read line,
and memory read multiple transactions. For memory read, the bits select whether to read a DWord, read to a
cache line boundary, or to fill the prefetch buffer. For memory read line and memory read multiple, the bits
select whether to read to a cache line boundary or to fill the prefetch buffer. In all cases, if the bits select to fill
the prefetch buffer, the maximum amount of data that is requested on the target interface is controllable by
the setting of the maximum memory read byte count bits of the Primary and Secondary Data Buffering
Control registers. When more than 512 bytes are requested, the bridge fetches data to fill the buffer and then
fetches more data to keep the buffer filled as sectors (128 bytes) are emptied and become free to use again.
Stopping the prefetching of data is controlled by the enable relaxed ordering bit of the Primary and Secondary
Data Buffering Control registers. If the bit is not set, prefetching stops when a posted write occurs on the
target bus or the originator disconnects or is disconnected after data transfer starts. If the bit is set, only the
originator disconnecting or the originator being disconnected will stop the transfers. When this bit is set, read
data bypasses posted writes that occur after the first data is prefetched.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM21P100BGC | PCI BUS CONTROLLER, PBGA304 |
| IBM25403GCX-3JC76C2 | RISC PROCESSOR, PQFP16 |
| IBM25405GP-3BA200C2 | RISC PROCESSOR, PBGA456 |
| IBM25EMPPC603EFG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| IBM25EMPPC603EBG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM24L5086 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM25403GCX-3BC80C2 | 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA |
| IBM25403GCX-3JC50C2 | 制造商:IBM 功能描述:403GCX-3JC50C2 |
| IBM25403GCX-3JC66C2 | 制造商:IBM 功能描述: |
| IBM25403GCX3JC76C2 | 制造商:IBM 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。