參數(shù)資料
型號(hào)： IBM21P100BGC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù)： 116/144頁
文件大小： 5197K
代理商： IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_pcix_regs.fm.01
October 15, 2001
Configuration Registers
Page 73 of 144
5.2.5.7 SERR# Disable Register
This register controls the assertion of the SERR# signal on the primary bus due to certain errors.
Address Offset
x‘5C’
Access
Read/Write
Reset Value
x‘00’
Re
s
e
rv
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d
P
E
RR#
o
n
P
o
s
te
d
W
ri
te
s
S
E
RR#
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is
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D
is
c
a
rd
ti
m
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S
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RR#
Di
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#
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Co
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c
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R
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try
Co
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t
S
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RR#
Di
s
a
b
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7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
7:5
RO
Reserved
4
RW
PERR# on Posted Writes SERR# Disable
Controls the SERR# assertion when a PERR# is detected on the destination bus on an error free posted write.
0
Assert SERR# and set bit 14 of the status register if the SERR# enable bit 8 in the command register
is set. Discard the delayed transaction.
1
Disable the assertion of SERR#.
3
RW
Primary Discard Timer SERR# Disable
Controls the SERR# assertion when the primary discard timer has expired.
0
Assert SERR# and update status bit 14 in the status register if the primary discard timer expires, the
SERR# enable bit 8 in the Command register is set, and bit 11 of the bridge control register is set. Dis-
card the delayed transaction and set bit 3 of the retry and timer status register.
1
Disable the assertion of SERR# if the primary discard timer expires. Discard the delayed transaction
and set bit 3 of the retry and timer status register.
2
RW
Secondary Discard Timer SERR# Disable
Controls the SERR# assertion when the secondary discard timer has expired.
0
Assert SERR# and update status bit 14 in the Status register if the secondary discard timer expires,
the SERR# enable bit 8 in the command register is set, and bit 11 of the bridge control register is set.
Discard the delayed transaction and set bit 2 of the retry and timer status register.
1
Disable the assertion of SERR# if the secondary discard timer expires. Discard the delayed transac-
tion and set bit 2 of the retry and timer status register.
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