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| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 141/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Configuration Registers
Page 96 of 144
ppb20_pcix_regs.fm.01
October 15, 2001
5.2.5.30 Miscellaneous Control Register 2
This register provides additional control over the memory read prefetch algorithm employed by the IBM 133
PCI-X Bridge R2.0 when both the primary and secondary buses are in PCI mode.
Address Offset
x‘B8’
Access
See individual fields.
Reset Value
b‘0000 0000 0000 00x0’
S
h
or
t
T
e
rm
C
ac
hi
ng
Reserved
P
rim
ar
y
P
re
fe
tch
P
er
sistenc
e
C
ontr
o
l
S
e
condar
y
P
re
fe
tch
P
er
s
istence
C
ontr
o
l
Reserved
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
15
R/W
Short Term Caching
This is used to control the Short Term Caching feature of the IBM 133 PCI-X Bridge R2.0.
0
Disabled
1
Enabled.
Note: A clear understanding all of the secondary side device’s device drivers and memory architectures, and
ensuring that the
PCI to PCI Bridge Architecture Specification as stated in Chapter 5, sections 5.1 Prefetching
Read Data and 5.6.2 Stale Data has been strongly adhered to, is required to prevent stale data from being
deliveredtothe master.
14:10
RW
Reserved
Modifying the contents of this field will have serious and unpredictable affects on the operation of the IBM 133
PCI-X Bridge R2.0
9
RW
Primary Prefetch Persistence Control
Affects the how the bridge reacts to target disconnect when prefetching data on the secondary bus for read
transactions that are initiated on the primary bus.
0
Discontinue prefetching when the target disconnects regardless of how much data has been buffered
1
Continue prefetching despite target disconnects until either: the byte count specified by Primary Data
Buffering Control Register has been prefetched, or the initiator disconnects.
8
RW
Secondary Prefetch Persistence Control
Affects the how the bridge reacts to target disconnect when prefetching data on the primary bus for read trans-
actions that are initiated on the secondary bus.
0
Discontinue prefetching when the target disconnects regardless of how much data has been buffered
1
Continue prefetching despite target disconnects until either: the byte count specified by Secondary
Data Buffering Control Register has been prefetched, or the initiator disconnects.
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