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參數(shù)資料
| 型號： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 5/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Clocking and Reset
Page 102 of 144
ppb20_clock_reset.fm.01
October 15, 2001
tie-up the signal, this may be useful for fixed frequency applications with simple clock generators or oscilla-
tors. A third possibility may be to use a ‘power good’ indicator, if the proper stability assurances can be made.
Other ways to provide the S_CLK_STABLE input signal may also be possible.
The S_CLK_STABLE input provides another measure of control for cases where the secondary bus mode
and clock frequency could vary from reset to reset, as in motherboard applications with pluggable slots. In
these applications the external clock generation circuitry will need to adapt to the changes along with the
bridge. If the S_CLK_STABLE signal is initially held low during reset, the bridge will not control the
S_PCIXCAP network and the clock generation circuitry is free to do its own mode and frequency determina-
tion sequence. The clock frequency may be adjusted based on the number of populated slots, determined by
the PRSNT pins of the bus. Once the frequency of the S_CLK input is stable, the clock circuit can assert the
S_CLK_STABLE signal to allow the bridge to complete the reset sequence. The clock generation circuitry
must ensure that the clock frequency it provides falls within the range that the bridge will ultimately determine
and broadcast on the initialization pattern. To do this, the clock generator may need to drive the proper values
on the S_SEL100 and S_PCIXCAP inputs, in addition to controlling the S_CLK_STABLE signal. A mismatch
between the broadcast initialization pattern and the actual operating mode and frequency of the bus is a
violation of the architecture and will cause unpredictable results.
6.5 Driver Impedance Selection
On the IBM 133 PCI-X Bridge R2.0, the output drivers for the bussed PCI/PCI-X interface signals are capable
of two different output impedances, a 40 ohm output impedance for point-to-point applications and a 20 ohm
output impedance for multi-point configurations. The output impedance for the primary and secondary inter-
faces is separately controlled. The bridge selects a default impedance value at the de-assertion of the bus
reset on the basis of the bus mode and frequency initialization pattern which was received on the primary
interface or generated on the secondary interface. It is assumed that if a bus is configured to be in the PCI-X
133 mode, it will be lightly loaded and therefore have a higher impedance. The drivers are put into
point-to-point mode for this case. For all other PCI-X and all PCI configurations, the bridge assumes that the
bus is more heavily loaded and has a lower impedance, so the drivers are set to multi-point mode.
There may be some applications for which these assumptions are inaccurate. For example, a conventional
PCI device may be connected in a point-to-point manner. For exceptions like this, two control input signals
are provided, P_DRVR_MODE for the primary interface and S_DRVR_MODE for the secondary interface.
When these inputs are pulled high, the bridge will change the output impedance of the drivers on their respec-
tive interfaces to the opposite state than was assumed by default, as shown in
Table 6-1. Driver Impedance Selection
Primary Bus Mode
Default Driver Mode
(P_DRVR_MODE=0)
Driver Mode if
P_DRVR_MODE=1
Secondary Bus
Mode
Default Driver Mode
(S_DRVR_MODE=0)
Driver Mode if
S_DRVR_MODE=1
Conventional PCI
Multi-point (20
)
Point-to-point (40
)
Conventional PCI
Multi-point (20
)
Point-to-point (40
)
PCI-X 66
Multi-point (20
)
Point-to-point (40
)
PCI-X 66
Multi-point (20
)
Point-to-point (40
)
PCI-X 100
Multi-point (20
)
Point-to-point (40
)
PCI-X 100
Multi-point (20
)
Point-to-point (40
)
PCI-X 133
Point-to-point (40
)
Multi-point (20
)
PCI-X 133
Point-to-point (40
)
Multi-point (20
)
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