- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67681 > IBM21P100BGC PCI BUS CONTROLLER, PBGA304 PDF資料下載
參數(shù)資料
| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 15/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_signals.fm.01
October 15, 2001
Signal Descriptions
Page 111 of 144
7.2 Secondary Interface Signals
Table 7-2. Secondary Interface Signal List (Page1of 2)
Signal Name
I/O
Width
Description
S_ACK64#
I/O
1
Acknowledge 64-Bit Transfer
Asserted by the currently addressed target on the secondary bus to indicate its willing-
ness to transfer data using 64 bits.
S_AD(63:00)
I/O
64
Multiplexed Address and Data
These signals are the 64-bit multiplexed address and data bus, shared by other devices
on the secondary bus. During a transaction, this bus contains the physical bus address,
attributes, or data, or it may be reserved.
S_C/BE(7:0)#
I/O
8
Multiplexed Bus Command and Byte Enables
During a transaction, these eight bits define the bus command, attributes, or byte
enables for the transfer. These signals are shared with other agents on the secondary
bus and at times may be reserved.
S_CLK
I
1
Clock
Received by the bridge and provides timing for all operations on the secondary interface.
S_DEVSEL#
I/O
1
Device Select
Asserted by the target on the secondary bus that decoded the address of the current
transaction as being within one of its address ranges.
S_DEVSEL# is monitored by the bridge when performing a secondary bus transaction
on behalf of a primary bus master.
S_DEVSEL# is driven by the bridge when a secondary bus master is performing a trans-
action on the secondary bus intended for a primary bus slave.
S_FRAME#
I/O
1
Cycle Frame
Defines the beginning and duration of each secondary bus transaction and is controlled
by the initiator of the operation.
S_FRAME# is driven by the bridge when performing a secondary bus transaction on
behalf of a primary bus master.
S_FRAME# is monitored by the bridge when a secondary bus master is performing a
transaction on the secondary bus.
S_GNT1REQ#
O
1
Grant 1
This is a dual-purpose signal:
When the bridge’s internal arbiter is enabled, this signal is used as a grant output, acti-
vatedbyathebridgetogrant theuse of thesecondary bus tothe master whorequested
the use with the S_REQ1GNT# signal.
When the internal arbiter is disabled, this signal is used by the bridge as its request out-
put signal.
S_GNT2# - S_GNT6#
O
5
Grants 2-6
Driven by the bridge's internal arbiter to grant usage of the secondary bus to the master
that activated the corresponding request signal.
S_IRDY#
I/O
1
Initiator Ready
This signal indicates the ability of the initiator on the secondary bus to complete the cur-
rent data phase of the transaction. It is used in conjunction with S_TRDY#.
S_IRDY# is driven by the bridge when performing a secondary bus transaction on behalf
of a primary bus master.
S_IRDY# is monitored by the bridge when a secondary bus master is performing a trans-
action on the secondary bus through the bridge.
S_LOCK#
I/O
1
Lock
Indicates that an atomic (unbroken) operation is required that may need multiple second-
ary bus transactions to complete.
The bridge drives S_LOCK# only to propagate an exclusive access from the primary bus
to the secondary bus and monitors S_LOCK# as part of that protocol.
When acting as a target on the secondary interface, the bridge ignores S_LOCK#.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25403GCX-3JC76C2 | RISC PROCESSOR, PQFP16 |
| IBM25405GP-3BA200C2 | RISC PROCESSOR, PBGA456 |
| IBM25EMPPC603EFG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| IBM25EMPPC603EBG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| IBM25EMPPC740LDBC4000 | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM24L5086 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM25403GCX-3BC80C2 | 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA |
| IBM25403GCX-3JC50C2 | 制造商:IBM 功能描述:403GCX-3JC50C2 |
| IBM25403GCX-3JC66C2 | 制造商:IBM 功能描述: |
| IBM25403GCX3JC76C2 | 制造商:IBM 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。