- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67681 > IBM21P100BGC PCI BUS CONTROLLER, PBGA304 PDF資料下載
參數(shù)資料
| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 17/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_signals.fm.01
October 15, 2001
Signal Descriptions
Page 113 of 144
7.3 Strapping Pins and Other Signals
Table 7-3. List of Strapping Pins and Other Signals (Page 1 of 2)
Signal Name
I/O
Width
Description
64_BIT_DEVICE#
I
1
Physical bus width of the PCI-X device
Used only when the IBM 133 PCI-X Bridge R2.0 is employed as the bus interface on a
PCI-X add-in card. The PCI-X Specification requires that such devices indicate the phys-
ical width of their bus in bit 16 of the PCI-X bridge status register. Bit 16 of the PCI-X
bridge status register is set directly from the inverse of the 64_BIT_DEVICE# pin. This
information is used solely by the configuration software; operation of the IBM 133 PCI-X
Bridge R2.0 is unaffected.
0
bit 16 of the PCI-X bridge status register is set to b’1’, indicating a 64 bit bus.
1
bit 16 of the PCI-X bridge status register is set to b’0’, indicating a 32 bit bus.
BAR_EN
I
1
Base Address Register Enable
Used to enable the base address register at reset or power up. The 64 bit register
located at offsets x'10' and x'14' is used to claim a 1 MB memory region when enabled.
The register returns all zeroes to read accesses and the associated memory region is
not claimed when disabled.
0
BAR disabled, register reads returns 0’s, no memory region claimed.
1
BAR enabled, bits 63:20 can be written by software to claim a 1 MB memory
region.
IDSEL_REROUTE_EN
I
1
IDSEL Reroute Enable
Used to enable the IDSEL reroute function at reset or power up. The reset value of the
secondary bus private device mask register is modified according to the tie value of the
IDSEL_REROUTE_EN pin. Note that configuration software can subsequently modify
the secondary bus private device mask register, regardless of how the
IDSEL_REROUTE_EN pin is tied.
0
reset value of the secondary bus private device mask register is x’00000000’.
1
reset value of the secondary bus private device mask register is x’22F20000’.
OPAQUE_EN
I
1
Opaque Region Enable
Used to enable the opaque memory region at reset or power up. The reset value of bit 0
of the opaque memory enable register is modified according to the tie value of the
OPAQUE_EN pin. The configuration software can subsequently modify bit 0 of the
opaque memory enable register, regardless of how the OPAQUE_EN pin is tied.
0
reset value of bit 0 of the opaque memory enable register is b’0’.
1
reset value of bit 0 of the opaque memory enable register is b’1’.
P_CFG_BUSY
I
1
Primary Configuration Busy
Controls the reset and power up value of bit 2 of the miscellaneous control register.
Used to sequence initialization with regard to the primary and secondary buses for appli-
cations that require access to the bridge configuration registers from the secondary bus.
When pulled high, the configuration commands received on the primary bus are retried
until such time as bit 2 of the miscellaneous control register is set to b‘0’ by a configura-
tion write initiated from the secondary bus. Applications that do not require access to the
bridge configuration registers from the secondary bus should pull this signal to ground.
0
reset value of bit 2 of the miscellaneous control register is b‘0’.
1
reset value of bit 2 of the miscellaneous control register is b‘1’.
P_DRVR_MODE
I
1
Primary driver mode control
Used to alter the output impedance of the primary bus PCI/PCI-X drivers, to account for
how many drops are on the bus. This line should be pulled through a resistor to a high or
a low as needed. Internal pull down.
0
use the default impedance value.
1
select the alternate impedance value.
RESERVED2
1
Reserved pin
RESERVED2 should be pulled to ground.
Note: Each strapping pin or reserved pin should have an unshared series resistor tying it to either ground or 3.3 V. The value of the
resistor may be selected to limit part number count, but the value should be greater than or equal to 100
and less than or equal to 5k.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25403GCX-3JC76C2 | RISC PROCESSOR, PQFP16 |
| IBM25405GP-3BA200C2 | RISC PROCESSOR, PBGA456 |
| IBM25EMPPC603EFG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| IBM25EMPPC603EBG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| IBM25EMPPC740LDBC4000 | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM24L5086 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM25403GCX-3BC80C2 | 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA |
| IBM25403GCX-3JC50C2 | 制造商:IBM 功能描述:403GCX-3JC50C2 |
| IBM25403GCX-3JC66C2 | 制造商:IBM 功能描述: |
| IBM25403GCX3JC76C2 | 制造商:IBM 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。