參數(shù)資料
型號： IBM21P100BGC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù)： 69/144頁
文件大?。?/td> 5197K
代理商： IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Bus Operation
Page 30 of 144
ppb20_operations.fm.01
October 15, 2001
Bit 2 of the Miscellaneous Control Register is b'0'.
On the secondary bus, the bridge responds to a Type 0 configuration transaction by accepting the transaction
when the following conditions are met during the address phase:
The command on S_C/BE(3:0)# indicates a configuration read or configuration write transaction;
S_AD(1:0) are b'00';and
S_IDSEL is asserted.
The function number is not decoded since the bridge is a single-function device. All configuration transactions
to the bridge are handled as DWord (single data phase) operations.
3.4.2 Type 1 to Type 0 Translation by Bridge
Type 1 configuration transactions are used to configure devices in a hierarchical bus structure having one or
more bridges. A bridge is the only type of device that should respond to a Type 1 configuration transaction.
Type 1configuration commands are used to access PCI/PCI-X devices that are located on a bus segment
other than the one where the Type 1 transaction is initiated.
The bridge performs a Type 1 to Type 0 translation when a Type 1 transaction is presented on the primary
interface that is destined for a device attached directly to the secondary interface. In this case, the bridge
must convert the configuration transaction to a Type 0 format so that the secondary bus device can accept it.
Type 1 to Type 0 translations are never performed in the upstream direction.
The bridge claims a Type 1 configuration transaction on its primary bus and translates it into a Type 0 trans-
action on the secondary bus when the following conditions are met during the address phase:
The command on P_C/BE(3:0)# indicates a configuration read or configuration write transaction;
P_AD(1:0) are b‘01’; and
The bus number on P_AD(23:16) is the same as the value in the secondary bus number register in the
bridge’s configuration space.
When the bridge translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it
performs the following translations to the address:
Sets S_AD(1:0) to b‘00’;
Decodes the device number specified and drives the bit pattern specified in
Table 3-5 on S_AD(31:16) for
use in the assertion of the device’s IDSEL signal;
Sets S_AD(15:11) to b‘00000’ if the secondary bus is operating in conventional PCI mode (in the PCI-X
mode, the device number is passed through unchanged); and
Leaves the function number and register number fields unchanged.
The bridge asserts a unique address signal based on the device number. These address signals may be
used as secondary bus IDSEL signals. Mapping of the address signals depends on the device number on
P_AD(15:11) of the Type1 configuration transaction.
Table 3-5 indicates how the bridge decodes the device number field. This default mapping may be modified
by the secondary bus private device mask register. See
Section 5.2.5.29 on page 94 for a description of how
the mapping may optionally be modified.
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