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| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 96/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_pcix_regs.fm.01
October 15, 2001
Configuration Registers
Page 55 of 144
5.2.4.19 Secondary Status Register
This register is similar in function and bit definition to the Status register. However, its bits reflect status condi-
tions of the secondary interface.
Address Offset
x‘1E’
Access
See individual bit fields. Writes are slightly different in that bits can be reset, but
not set. A bit is reset whenever the register is written, and the data in the corre-
sponding bit location is a ‘1’.
Reset Value
x‘02A0’ in the PCI mode, x‘0220’ in the PCI-X mode
De
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RR#
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Reserved
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
15
RW
Detected Parity Error Status
0
Device did not detect a parity error.
1
Device detected a parity error.
14
RW
Signaled System Error Status
0
Device did not receive a SERR# signal on the secondary interface.
1
Device received a SERR# signal on the secondary interface.
13
RW
Received Master Abort Status
0
Bus master transaction was not terminated with bus master abort.
1
Bus master transaction terminated with bus master abort.
12
RW
Received Target Abort Status
0
Bus master transaction was not terminated by target abort.
1
Bus master transaction terminated by target abort.
11
RW
Signaled Target Abort Status
0
Target device did not terminate a transaction with target abort.
1
Target device terminated a transaction with target abort.
10:9
RO
Device Select (DEVSEL#) Timing Status
01
Medium.
8
RW
Data Parity Status
0
No data parity errors encountered.
1
Data parity errors encountered (this bit for bus masters only).
7
RO
Fast Back-to-Back Capable
0
Target not capable of accepting fast back-to-back transactions in the PCI-X mode.
1
Target capable of accepting fast back-to-back transactions in conventional mode.
This bit isset toab‘1’ by hardware when the secondary interface is in the PCI mode and is set to a b‘0’ when
the secondary interface is in the PCI-X mode.
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