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| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 9/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Clocking and Reset
Page 106 of 144
ppb20_clock_reset.fm.01
October 15, 2001
6.9 Secondary Device Masking
The IBM 133 PCI-X Bridge R2.0 supports the masking of secondary devices through configuration/power
strapping of the secondary bus private device mask register. The process of converting Type 1 configuration
transactions to Type 0 configuration transactions is modified by the contents of the secondary bus private
device mask register. A configuration transaction that targets a device masked by this register is routed to
device 15. Secondary bus architectures which are designed to support masking of devices should not imple-
ment a device number 15 (i.e., S_AD(31)).
The device mask bit options (device numbers 1, 4, 5, 6, 7, 9, and 13) defined by the bridge allow architectures
to support private device groupings that use a single or multiple interrupt binding per
Table 9-1 of the
PCI-to-PCI Bridge specification.
6.10 Handling of Address Phase Parity Errors
When an address parity error is detected by the bridge, the transaction will not be claimed (by not asserting
DEVSEL#) and is allowed to terminate with a master abort. The bridge will detect address parity errors for all
transactions on both the primary and secondary interfaces. The result of an address parity error will be
controlled by the parity error response bits in both the command register and the bridge control register.
6.11 Optional Base Address Register
The 64 bit Base Address register located in the bridge configuration space at offsets x'10' and x'14' can
optionally be used to acquirea1MB memory region at system initialization. ThePCI specificationcalls forthe
region that is defined by this register to be used by the bridge itself. The IBM 133 PCI-X Bridge uses this
register to claim an additional prefetchable memory region for the secondary bus. When used in conjunction
with the secondary device masking, this allows for the acquisition of memory space for private devices that
are not otherwise viewable by the system software.
This 64 bit base address register and the memory space defined by it are enabled by the strapping pin,
BAR_EN. When BAR_EN is pulled low, this register location returns zeros for reads and cannot be written.
When BAR_EN is pulled high, the upper memory base address register and lower memory base address
registers combined specify address bits 63:20 of a memory region. Memory accesses on the primary bus are
compared against this register, if address bits 63:20 are equal to bits 63:20 of the address defined by the
combination of the lower memory base address register and the upper memory base address register, the
access is claimed by the bridge and passed through to the secondary bus. Memory accesses on the
secondary bus are also compared against this register, if address bits 63:20 are equal to bits 63:20 of the
address defined by the combination of the lower memory base address register and the upper memory base
address register, the access is ignored by the bridge.
6.12 Optional Configuration Register Access from the Secondary Bus
On the secondary bus, the bridge responds to a Type 0 configuration transaction by accepting the transaction
when the following conditions are met during the address phase:
The command on S_C/BE(3:0)# indicates a configuration read or configuration write transaction,
S_AD(1:0) are b'00', and
S_IDSEL is asserted.
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