參數(shù)資料
型號(hào)： IBM21P100BGC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù)： 128/144頁
文件大小： 5197K
代理商： IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Configuration Registers
Page 84 of 144
ppb20_pcix_regs.fm.01
October 15, 2001
5.2.5.19 PCI-X Secondary Status Register
This register reports status information about the secondary interface.
Address Offset
x‘82’
Access
See individual bit descriptions. Reads to this register behave normally. Writes are
slightly different in that bits can be reset, but not set. A bit is reset whenever the
register is written, and the data in the corresponding bit location is a ‘1’.
Reset Value
x‘0003’
Re
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req
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15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
15:9
RO
Reserved.
8:6
RO
Secondary Clock Frequency
This register enables the configuration software to determine to what mode and (in the PCI-X mode) what
frequency the bridge set the secondary bus to the last time the secondary RST# was asserted. This is the
same information the bridge used to create the PCI-X initialization pattern on the secondary bus the last time
the secondary RST# was asserted.
Value
Max Clock Frequency (MHz) Minimum Clock Period (ns)
000
Conventional mode.
N/A
001
66
15
010
100
10
011
133
7.5
100
Reserved.
101
Reserved.
110
Reserved.
111
Reserved.
5
RW
Split Request Delayed
This bit is set any time the bridge has a request to forward a transaction to the secondary bus, but cannot
because there is not enough room within the limit specified in the split transaction commitment limit field in
the downstream split transaction control register. It is used by algorithms that optimize the setting of the
downstream split transaction commitment limit register.
0
The bridge has not delayed a split request.
1
The bridge has delayed a split request.
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