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| 型號(hào)： | IBM21P100BGC |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 18/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Signal Descriptions
Page 114 of 144
ppb20_signals.fm.01
October 15, 2001
S_DRVR_MODE
I
1
Secondary driver mode control
Used to alter the output impedance of the secondary bus PCI/PCI-X drivers, to account
for how many drops are on the bus. This line should be pulled through a resistor to a
high or a low as needed. Internal pull down.
0
use default impedance value.
1
select alternate impedance value.
S_CLK_STABLE
I
1
S_CLK Input Stable
Indicates when the S_CLK input to the bridge is stable. It is used to determine when the
S_RST# signal may be de-asserted.
0
S_CLK input is not yet stable.
1
S_CLK input is stable.
S_IDSEL
I
1
Initialization Device Select
Used as a chip select during configuration read and write transactions on the secondary
bus. Applications that do not require access to the bridge configuration registers from the
secondary bus should pull this pin low.
S_INT_ARB_EN#
I
1
Internal Arbiter Enable
Used to choose between the internal arbiter and external arbiter for the secondary bus.
0
Use the internal arbiter.
1
Disable the internal arbiter, use an external arbiter.
S_PCIXCAP
I
1
Secondary Bus PCI-X Capable
Used in conjunction with the S_SEL100 signal to determine the operating frequency and
mode of the secondary interface.
S_PCIXCAP_PU
O
1
S_PCIXCAP Pull-up Driver
Part of a programmable pull-up circuit used to detect the three possible states of the
S_PCIXCAP input signal. A 1k
resistor must be placed on the board and wired
between this signal and S_PCIXCAP.
S_SEL100
I
1
Secondary Bus 100MHz Indicator
Used to choose between 100MHz and 133MHz maximum operating frequency on the
secondary interface when in the PCI-X mode. It has no meaning in the PCI mode, but
should be tied to a stable value.
0133MHz.
1100MHz.
Total
14
Table 7-3. List of Strapping Pins and Other Signals (Page 2 of 2)
Signal Name
I/O
Width
Description
Note: Each strapping pin or reserved pin should have an unshared series resistor tying it to either ground or 3.3 V. The value of the
resistor may be selected to limit part number count, but the value should be greater than or equal to 100
and less than or equal to 5k.
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