- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67681 > IBM21P100BGC PCI BUS CONTROLLER, PBGA304 PDF資料下載
參數(shù)資料
| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 72/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)當(dāng)前第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_ordering.fm.01
October 15, 2001
Transaction Ordering
Page 33 of 144
4. Transaction Ordering
To maintain data coherence and consistency, the IBM 133 PCI-X Bridge R2.0 complies with the ordering
rules set forth in the
PCI Local Bus Specification, Revision 2.2 for the PCI mode and the PCI-X Addendum to
the PCI Local Bus Specification, Revision 1.0 for the PCI-X mode.
This chapter describes the ordering rules that control transaction forwarding across the bridge. For a more
detailed discussion of transaction ordering see Appendix E of the
PCI Local Bus Specification, Revision 2.2
for the PCI mode and Section 8.4.4 of the
PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0
for the PCI-X mode.
4.1 General Ordering Guidelines
Independent transactions on the primary and secondary buses have a relationship only when those transac-
tions cross the IBM 133 PCI-X Bridge R2.0.
The following general ordering guidelines govern transactions crossing the bridge:
Requests terminated with target retry can be accepted and completed in any order with respect to other
transactions that have been terminated with target retry. If the order of delayed or split requests is impor-
tant, the initiator should not start a second delayed or split transaction until the first transaction has been
completed. If more than one delayed or split transaction is initiated, the initiator should repeat all retried
requests, using some fairness algorithm. Repeating a delayed or split transaction cannot be contingent
upon the completion of another delayed transaction; otherwise, a deadlock can occur.
Write transactions flowing in one direction have no ordering requirements with respect to write transac-
tions flowing in the opposite direction. The bridge can accept posted write transactions on both interfaces
at the same time, and also can initiate posted write transactions on both interfaces at the same time.
The acceptance of posted memory or memory write transactions as a target can never be contingent on
the completion of a non-locked, non-posted transaction as a master. This is true of the bridge and must
also be true of other bus agents; otherwise, a deadlock can occur.
The bridge accepts posted memory or memory write transactions, regardless of the state of completion of
any delayed or split transactions being forwarded across the bridge.
4.2 Ordering Rules
Table 4-1 and Table 4-2 describe the ordering rules for the IBM 133 PCI-X Bridge R2.0 in the PCI-X and the
PCI modes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25403GCX-3JC76C2 | RISC PROCESSOR, PQFP16 |
| IBM25405GP-3BA200C2 | RISC PROCESSOR, PBGA456 |
| IBM25EMPPC603EFG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| IBM25EMPPC603EBG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| IBM25EMPPC740LDBC4000 | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM24L5086 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM25403GCX-3BC80C2 | 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA |
| IBM25403GCX-3JC50C2 | 制造商:IBM 功能描述:403GCX-3JC50C2 |
| IBM25403GCX-3JC66C2 | 制造商:IBM 功能描述: |
| IBM25403GCX3JC76C2 | 制造商:IBM 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。