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| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 55/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
General Information
Page 18 of 144
ppb20_intro.fm.01
October 15, 2001
2.5 Operation Overview
This section gives a brief description of operation for various aspects of the IBM 133 PCI-X Bridge R2.0. More
detailed information on these topics can be found in subsequent chapters.
2.5.1 Supported Modes
The IBM 133 PCI-X Bridge R2.0 is a full-function transparent PCI-X to PCI-X bridge. As such, either interface
may be configured to operate using the conventional PCI bus protocol or the PCI-X bus protocol. In mixed-
mode configurations, the IBM 133 PCI-X Bridge R2.0 hardware handles the conversion from one protocol to
the other.
Any allowed bus clock frequency range for a particular mode may be used, up to 66 MHz for PCI mode and
up to 133 MHz per section 9.4.1 of the PCI-X 1.0a specification. Operation at a particular speed depends on
the bus topology and loading. Since the two clock domains are asynchronous and independent, a different
bus speed may be used on each interface. Speed-matching is accomplished via the buffering structure of the
IBM 133 PCI-X Bridge R2.0 design.
The IBM 133 PCI-X Bridge R2.0 implements a 64-bit bus on both interfaces. The PCI architecture also allows
either side to be connected to a 32-bit bus or to 32-bit devices. Full 64-bit addressing capability is also
provided, including support for dual address cycles (DAC).
Note: The IBM 133 PCI-X Bridge R2.0 uses the 3.3 V signaling environment and is not tolerant of 5 V signal
levels. When the IBM 133 PCI-X Bridge R2.0 is mounted on an adapter card, the card must use the 3.3 V
connector keying scheme.
2.5.2 Buffer Structure
The IBM 133 PCI-X Bridge R2.0 contains two symmetric sets of buffers with associated queues, one for
upstream transactions and the other for downstream transactions.
2.5.2.1 Burst Read Buffers
Each burst read buffer shown in
Figure 2-1 contains 4 KB to hold data from memory burst read transactions.
Each buffer is logically divided into eight independent 512-byte buffers to allow for multi-threading. Each 512-
byte buffer has a read queue providing up to eight active read transactions in each direction.
Every 512-byte buffer is further divided into four 128-byte subsections. Activity generally occurs on these
128-byte boundaries. Filling and/or emptying 128 bytes causes bus transactions to be initiated. While each
read queue entry has up to 512 bytes of buffer space associated with it, to keep data flowing efficiently the
128-byte subsections are re-used as needed when they are emptied. This means that when the primary and
secondary interfaces are running at similar frequencies and there is little bus contention, long transfers can
proceed without disconnection, after the initial latency needed to fill the first 128-byte subsection. For large
transfers when the two buses are running at vastly dissimilar frequencies, disconnections may occur on the
faster bus as often as every 128 bytes as the 512-byte buffer becomes completely full or empty.
2.5.2.2 Posted Write Buffers
The posted write buffers each have a capacity of 1 KB to hold data from posted memory write transactions.
Each is logically divided into eight independent 128-byte segments to allow transactions to be issued on the
destination bus before they have been completed on the originating bus. Unlike the burst read buffers, the
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