參數(shù)資料
型號(hào)： IBM21P100BGC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù)： 83/144頁
文件大小： 5197K
代理商： IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_pcix_regs.fm.01
October 15, 2001
Configuration Registers
Page 43 of 144
5.2.4.3 Command Register
This register provides a variety of configurable parameters defining the device’s interaction with the PCI bus.
Address Offset
x‘04’
Access
See individual bit fields.
Reset Value
x‘0000’
Reserved
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15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
FieldNameand Description
15:10
RO
Reserved
9
RO
Fast Back-to-Back Control
0
Fast back-to-back transactions are allowed only for the same agent
This bit is ignored in the PCI-X mode
8
RW
System Error Control
0
Disable the SERR# output driver.
1
Enable the SERR# output driver.
7
RO
Wait Cycle Control
0
Disable Address/Data stepping.
This bit is ignored in the PCI-X mode.
6
RW
Parity Error Response
0
Ignore detected parity errors.
1
Respond to detected parity errors.
Controls the response to address and data parity errors on the primary interface. If this bit is set, the bridge
must take its normal action when a parity error is detected. If this bit is cleared, the bridge must ignore any par-
ity errors that it detects and continue normal operation. In either case, the parity error detected bit of the Status
register gets set if an address or data parity error is detected.
5
RW
VGA Palette Snoop Control
0
Disable palette snooping, treat palette accesses like all other accesses.
1
Enable palette snooping.
4
RO
Memory Write and Invalidate Control
0
Disable MWI.
This bit is ignored in the PCI-X mode.
3
RO
Special Cycles Control
0
Ignore special cycle operations.
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