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參數(shù)資料
| 型號： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 19/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_signals.fm.01
October 15, 2001
Signal Descriptions
Page 115 of 144
7.4 Test Signals
Table 7-4.ListofTestSignals
Signal Name
I/O
Width
Description
JTG_TCK
I
1
JTAG Test Clock
Used to clock state information and test data into and out of the bridge during operation
of the IEEE 1149.1 test access port (TAP). Internal pull-up.
JTG_TDI
I
1
JTAG Test Data Input
Used to serially shift test data and test instructions into the bridge during TAP operation.
Internal pull-up.
JTG_TDO
O
1
JTAG Test Output
Used to serially shift test data and test instructions out of the bridge during TAP opera-
tion.
JTG_TMS
I
1
JTAG Test Mode Select
Used to control the state of the TAP controller within the bridge. Internal pull-up.
JTG_TRST#
I
1
JTAG Test Reset
Provides an asynchronous initialization of the TAP controller within the bridge. Internal
pull-up.
T_DI1#
I
1
Driver Inhibit 1
Used to tri-state the outputs of non-test drivers during manufacturing test. It must be tied
high for normal system operation. Internal pull-up.
T_DI2#
I
1
Driver Inhibit 2
Used to tri-state the outputs of the test drivers during manufacturing test. It must be tied
high for normal system operation. Internal pull-up.
T_MODECTL
I
1
Driver Mode Control
Used to control the PCI/PCI-X driver impedance during manufacturing test. It should be
tied low for normal system operation.
T_RI#
I
1
Receiver Inhibit
Used to gate all receivers during manufacturing test. It must be tied high for normal sys-
tem operation.
TEST_CE0
I
1
Test Mode Enable
Used to enable scan testing of the bridge device during manufacturing test. It must be
tied low for normal system operation. Internal pull-down.
XCLK_OUT
O
1
PLL Output Monitor
This signal may be used to monitor the output of the phase-locked loop circuits for the
primary and secondary interfaces. During normal system operation, this output is in a
high-impedance state and should be pulled down on the board.
Total
11
Note: With the bridge containing internal pull-up resistors on TDI, TMS, TRST#, and TCK, system designers need to assure voltage
dividers are not generated by the possible implementation of pull-down resistors as defined in sections 4.3.3 and 4.4.1 of the PCI 2.2
specification.
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