![](http://datasheet.mmic.net.cn/100000/IBM21P100BGC_datasheet_3492192/IBM21P100BGC_94.png)
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Configuration Registers
ppb20_pcix_regs.fm.01
October 15, 2001
5.2.5.29 Secondary Bus Private Device Mask Register
This register provides a means to implement private devices on the secondary PCI bus. The process of
converting Type 1 configuration transactions to Type 0 configuration transactions is modified by the contents
of this register. A configuration transaction that targets a device masked by this register is rerouted to device
15. Setting the secondary bus private device mask register to zeros disables this function.
Address Offset
x‘B0’
Access
R/W
Reset Value
x‘0000 0000’ When IDSEL_REROUTE_EN (pin AC22) is tied low. See
Reset Value
x‘22F2 0000’ When IDSEL_REROUTE_EN (pin AC22) is tied high. See
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9
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
31:30
RW
Reserved.
Masking for devices 14 and 15 is not implemented. Operation of the IBM 133 PCI-X Bridge R2.0 is unaffected
by the value of these bits.
29
RW
PrivateDeviceMask13
0
Rerouting disabled for device 13.
1
Block assertion of S_AD(pin 29) for configuration transactions to device 13, assert S_AD(pin 31)
instead.
28:26
RW
Reserved.
Masking for devices 12, 11, and 10 is not implemented. Operation of the IBM 133 PCI-X Bridge R2.0 is unaf-
fected by the value of these bits.
25
RW
PrivateDeviceMask9
0
Rerouting disabled for device 9.
1
Block assertion of S_AD(pin 25) for configuration transactions to device 9, assert S_AD(pin 31)
instead.
24
RW
Reserved
Masking for devices 8 is not implemented. Operation of the IBM 133 PCI-X Bridge R2.0 is unaffected by the
value of this bit.
23
RW
PrivateDeviceMask7
0
Rerouting disabled for device 7.
1
Block assertion of S_AD(pin 23) for configuration transactions to device 7, assert S_AD(pin 31)
instead.