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參數(shù)資料
| 型號(hào)： | ICS1892 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁數(shù)： | 109/148頁 |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892 |
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Chapter 9
Pin Diagram, Listings, and Descriptions
ICS1892, Rev. D, 2/26/01
February 26, 2001
109
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
9.2.4
MAC/Repeater Interface Pins
This section lists pin descriptions for each of the following interfaces
Section 9.2.4.1, “MAC/Repeater Interface Pins for Media Independent Interface”
Section 9.2.4.2, “MAC/Repeater Interface Pins for 100M Symbol Interface”
Section 9.2.4.3, “MAC/Repeater Interface Pins for 10M Serial Interface”
Section 9.2.4.4, “MAC/Repeater Interface Pins for Link Pulse Interface”
9.2.4.1
MAC/Repeater Interface Pins for Media Independent Interface
Table 9-6
lists the MAC/Repeater Interface pin descriptions for the MII.
Table 9-6.
MAC/Repeater Interface Pins: Media Independent Interface (MII)
Pin
Name
Pin
Number
Pin
Type
Pin Description
COL
49
Output
Collision (Detect).
The ICS1892 asserts a signal on the COL pin when the ICS1892 detects
receive activity while transmitting (that is, while the TXEN signal is
asserted by the MAC/repeater, that is, when transmitting). When the
mode is:
10Base-T, the ICS1892 detects receive activity by monitoring the
un-squelched MDI receive signal.
100Base-TX, the ICS1892 detects
receive activity when there are two
non-contiguous zeros in any 10-bit symbol derived from the MDI
receive data stream.
Note:
1. The signal on the COL pin is not synchronous to either RXCLK or
TXCLK.
2. In full-duplex mode, the COL signal is disabled and always remains
low.
3. The COL signal is asserted as part of the signal quality error (SQE)
test. This assertion can be suppressed with the SQE Test Inhibit bit (bit
18.2).
CRS
50
Output
Carrier Sense.
In half-duplex mode, the ICS1892 asserts a signal on the CRS pin
when the ICS1892 detects either receive or transmit activity.
In full-duplex mode and Repeater mode, the ICS1892 asserts a signal
on the CRS pin only when the ICS1892 detects receive activity.
Note:
The signal on the CRS pin is not synchronous to either RXCLK or
TXCLK.
MDC
31
Input
Management Data Clock.
The ICS1892 uses the signal on the MDC pin to synchronize the transfer
of management information between the ICS1892 and the Station
Management Entity (STA), using the serial MDIO data line. The MDC
signal is sourced by the STA.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
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