- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360744 > ICS1892 10Base-T/100Base-TX Integrated PHYceiver PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS1892 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁數(shù)： | 27/148頁 |
| 文件大小： | 816K |
| 代理商： | ICS1892 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁
Chapter 6
Interface Overviews
ICS1892, Rev. D, 2/26/01
February 26, 2001
27
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
6.3
10M Serial Interface
When the Mac/Repeater Interface is configured as a 10M Serial Interface, the ICS1892 and the
MAC/repeater exchange a framed, serial bit stream along with associated control signals. The 10M Serial
Interface configuration is ideally suited to applications that already incorporate a serial 10Base-T MAC with
a standard ‘7-wire’ interface. The ICS1892 MAC/Repeater Interface can be configured for 10M Serial
Interface operations, as determined by ICS1892 configuration functions. When the HW/SW pin is set for:
Hardware mode, the 10M Serial Interface is selected when the following are true:
– The MII/SI input pin is logic one (that is, the selection is for a Serial Interface).
– The 10/100SEL input pin is logic zero (that is, the selection is for 10M operations).
– The 10/LP input pin is logic zero
Software mode, the 10M Serial Interface is selected when the following are true:
– The MII/SI input pin is logic one (that is, the selection is for a Serial Interface).
– The Control Register Data Rate bit (bit 0.13) is logic zero (that is, the selection is for 10M operations).
– The 10/LP input pin is logic zero
Note:
In software mode, the 10/100SEL pin becomes an output that indicates the state of bit 0.13.
The 10M Serial Interface has two data paths: one for data transmission and one for data reception. Each
data path exchanges a serial bit stream with the MAC/repeater at a 10-MHz clock rate. A benefit of using
the 10M Serial Interface – in contrast to the 10M MII Interface – is a reduction in the bit latency through the
ICS1892. This reduction is attributed to the elimination of both parallel-to-serial and serial-to-parallel data
conversions.
The 10M Serial Interface consists of the following nine signals: 10TCLK, 10TXEN, 10TD, 10RCLK,
10RXDV, 10RD, 10CRS, 10COL, and LSTA. (When the ICS1892 MAC/Repeater Interface is configured for
10M Serial operations, both its default MII pin names and their associated functions are redefined. For
more information, see
Section 9.2.4.3, “MAC/Repeater Interface Pins for 10M Serial Interface”
.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。