參數(shù)資料
型號(hào)： ICS1892
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 87/148頁
文件大?。?/td> 816K
代理商： ICS1892
Chapter 8
Management Register Set
ICS1892, Rev. D, 2/26/01
February 26, 2001
87
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.11.1
Command Override Write Enable (bit 16.15)
The Command Override Write Enable bit provides an STA the ability to alter the Command Override Write
(CW) bits located throughout the MII Register set. A two-step process is required to alter the value of a CW
bit:
1.
2.
Step one is to issue a Command Override, that is, bit 16.15 is set to logic one.
Step two immediately follows, which is a write to the CW bit that you wish to change. (The Command
Override Write Enable bit is a Self-Clearing bit that is automatically reset to logic zero after the next MII
write, thereby allowing only one subsequent write to alter a CW bit.)
8.11.2
ICS Reserved (bits 16.14:11)
ICS is reserving these bits for future use. Functionally, these bits are equivalent to IEEE Reserved bits.
When one of these reserved bits is:
Read by an STA, the ICS1892 returns a logic zero.
Written to by an STA, the STA must use the default value specified in this data sheet.
ICS uses some of these reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1892, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA
always write the default value of any reserved bits during all management register write operations.
8.11.3
PHY Address (bits 16.10:6)
These five bits hold the Serial Management Port Address of the ICS1892. During either a hardware reset
or a power-on reset, the PHY address is read from the LED interface. (For information on the LED
interface, see
Section 6.9, “Status Interface”
and
Section 9.2.2, “Multi-Function (Multiplexed) Pins: PHY
Address and LED Pins”
). The PHY address is then latched into this register. (The value of each of the PHY
Address bits is unaffected by a software reset.)
8.11.4
Stream Cipher Scrambler Test Mode (bit 16.5)
The Stream Cipher Scrambler Test Mode bit is used to force the ICS1892 to lose LOCK, thereby requiring
the Stream Cipher Scrambler to resynchronize.
8.11.5
ICS Reserved (bit 16.4)
See
Section 8.11.2, “ICS Reserved (bits 16.14:11)”
, the text for which also applies here.
8.11.6
NRZ/NRZI Encoding (bit 16.3)
This bit allows an STA to control whether NRZ (Not Return to Zero) or NRZI (Not Return to Zero, Invert on
One) encoding is applied to the serial transmit data stream in 100Base-TX mode. When this bit is logic:
Zero, the ICS1892 encodes the serial transmit data stream using NRZ encoding.
One, the ICS1892 encodes the serial transmit data stream using NRZI encoding.
相關(guān)PDF資料
PDF描述
ICS1892Y 10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-10 10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-14 10Base-T/100Base-TX Integrated PHYceiver
ICS1893AF 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
ICS1893Y-10 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1892Y 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-10 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-14 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1893 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893_09 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
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