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參數(shù)資料
| 型號(hào)： | ICS1892 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁(yè)數(shù)： | 55/148頁(yè) |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892 |
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Chapter 7
Functional Blocks
ICS1892, Rev. D, 2/26/01
February 26, 2001
55
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
7.6
Functional Block: Management Interface
As part of the MII, the ISO/IEC 8802-3 standard specifies a two-wire serial management interface and
protocol. This interface is used to exchange control, status, and configuration information between the
Station Management entity (STA) and the physical layer device (PHY). For using this management
interface, the ISO/IEC standard specifies the following:
A set of registers (
Section 7.6.1, “Management Register Set Summary”
)
The frame structure (
Section 7.6.2, “Management Frame Structure”
)
The protocol
The ICS1892 implementation of the management interface complies fully with the ISO/IEC standard. It
provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the data transfers.
These pins remain active in all MAC/Repeater Interface modes (that is, the 10/100 MII, 100M Symbol, 10M
Serial, and Link Pulse interface modes).
7.6.1
Management Register Set Summary
The ICS1892 implements a Management Register set that adheres to the ISO/IEC standard. This register
set (discussed in detail in
Chapter 8, “Management Register Set”
) includes the mandatory ‘Basic’ Control
and Status registers as well as the ICS-specific Extended registers.
7.6.2
Management Frame Structure
The Management Interface is a bi-directional serial interface to exchange configuration, control, and status
data between a PHY such as the ICS1892 and the STA. The PHY and STA exchange data by using the
defined register set. The STA initiates all transactions.
The ISO/IEC specification defines a Management Frame Structure for the serial data stream. The ICS1892
complies with the defined frame structure and protocol.
Table 7-2
summarizes the Management Frame
Structure.
Note:
The Management Frame Structure starts from and returns to an IDLE condition. However, the
IDLE periods are not part of the Management Frame Structure.
Table 7-2.
Management Frame Structure Summary
Frame Field
Data
Comment
Acronym
Frame Function
PRE
Preamble (Bit 1.6)
11..11
32 ones
SFD
Start of Frame
01
2 bits
OP
Operation Code
10/01 (read/write)
2 bits
PHYAD
PHY Address (Bits 16.10:6)
AAAAA
5 bits
REGAD
Register Address
RRRRR
5 bits
TA
Turnaround
Z0/10 (read/write)
2 bits
DATA
Data
DDD..DD
16 bits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
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