參數(shù)資料
型號： ICS1892
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 93/148頁
文件大?。?/td> 816K
代理商： ICS1892
Chapter 8
Management Register Set
ICS1892, Rev. D, 2/26/01
February 26, 2001
93
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.12.8
Halt Symbol (bit 17.6)
The Halt Symbol bit indicates to an STA the detection of an Halt Symbol in a 100Base data stream by the
ICS1892.
During reception of a valid packet, the ICS1892 examines each symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. In addition, it looks for special symbols such as the Halt
Symbol. If a Halt Symbol is encountered, the ICS1892 indicates this condition to the MAC/repeater.
If this bit is set to a logic:
Zero, it indicates a Halt Symbol has not been detected since the last read of this register.
One, it indicates a Halt Symbol was detected in the packet since the last read of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see
Section
8.1.4.1, “Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
Note:
This bit has no definition in 10Base-T mode.
8.12.9
Premature End (bit 17.5)
The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream
by the ICS1892.
During reception of a valid packet, the ICS1892 examines each symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. If two consecutive Idles are encountered it indicates
this condition to the MAC/repeater by setting this bit.
If this bit is set to a logic:
Zero, it indicates a Premature End condition has not been detected since the last read of this register.
One, it indicates a Premature End condition was detected in the packet since the last read of this
register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see
Section
8.1.4.1, “Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
Note:
This bit has no definition in 10Base-T mode.
8.12.10
Auto-Negotiation Complete (bit 17.4)
The Auto-Negotiation Complete bit is used to indicate to an STA the completion of the Auto-Negotiation
process. When this bit is set to logic:
Zero, it indicates that the auto-negotiation process is either not complete or is disabled by the Control
Register’s Auto-Negotiation Enable bit (bit 0.12)
One, it indicates that the ICS1892 has completed the auto-negotiation process and that the contents of
Management Registers 4, 5, and 6 are valid.
8.12.11
100Base-TX Signal Detect (bit 17.3)
The 100Base-TX Signal Detect bit indicates either the presence or absence of a signal on the Twisted-Pair
Receive pins (TP_RXP and TP_RXN) in 100Base-TX mode. This bit is logic:
Zero when no signal is detected on the Twisted-Pair Receive pins and logic.
One when a signal is present on these pins.
8.12.12
Jabber Detect (bit 17.2)
Bit 17.2 is functionally identical to bit 1.1. The Jabber Detect bit indicates whether a jabber condition has
occurred. This bit is a 10Base-T function.
相關(guān)PDF資料
PDF描述
ICS1892Y 10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-10 10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-14 10Base-T/100Base-TX Integrated PHYceiver
ICS1893AF 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
ICS1893Y-10 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1892Y 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-10 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-14 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1893 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893_09 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
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