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| 型號(hào)： | ICS1892 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁(yè)數(shù)： | 62/148頁(yè) |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892 |
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ICS1892, Rev. D, 2/26/01
February 26, 2001
62
Chapter 8
Management Register Set
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.2
Register 0: Control Register
Table 8-5
lists the bits for the Control Register, a 16-bit register used to establish the basic operating modes
of the ICS1892.
The Control Register is accessible through the MII Management Interface.
Its operation is independent of the MAC/Repeater Interface configuration.
It is fully compliant with the ISO/IEC Control Register definition.
Note:
For an explanation of acronyms used in
Table 8-5
, see
Chapter 1, “Abbreviations and Acronyms”
.
Whenever the PHY address of
Table 8-16
:
Is equal to 00000 (binary), the Isolate bit 0.10 is logic one.
Is not equal to 00000, the Isolate bit 0.10 is logic zero.
As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
8.2.1
Reset (bit 0.15)
This bit controls the software reset function. Setting this bit to logic one initiates an ICS1892 software reset
during which all Management Registers are set to their default values and all internal state machines are
set to their idle state. For a detailed description of the software reset process, see
Section 5.1.2.3,
“Software Reset”
.
During reset, the ICS1892 leaves bit 0.15 set to logic one and isolates all STA management register
accesses for 640 ns. However, the reset process is not complete until bit 0.15 (a Self-Clearing bit), is set to
logic zero, which indicates the reset process is terminated.
Table 8-5.
Control Register (Register 0 [0x00]
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
0.15
Reset
No effect
ICS1892 enters Reset
mode
R/W
SC
0
3
0.14
Loopback enable
Disable Loopback mode
Enable Loopback mode
R/W
–
0
0.13
Data rate select
10 Mbps operation
100 Mbps operation
R/W
–
1
0.12
Auto-Negotiation enable
Disable Auto-Negotiation Enable Auto-Negotiation
R/W
–
1
0.11
Low-power mode
Normal power mode
Low-power mode
R/W
–
0
0/4
0.10
Isolate
No effect
Isolate ICS1892 from MII
R/W
–
0/1
0.9
Auto-Negotiation restart
No effect
Restart Auto-Negotiation
R/W
SC
0
0.8
Duplex mode
Half-duplex operation
Full-duplex operation
R/W
–
0
0.7
Collision test
No effect
Enable collision test
R/W
–
0
0
0.6
IEEE reserved
Always 0
N/A
RO
–
0
0.5
IEEE reserved
Always 0
N/A
RO
–
0
0.4
IEEE reserved
Always 0
N/A
RO
–
0
0.3
IEEE reserved
Always 0
N/A
RO
–
0
0
0.2
IEEE reserved
Always 0
N/A
RO
–
0
0.1
IEEE reserved
Always 0
N/A
RO
–
0
0.0
IEEE reserved
Always 0
N/A
RO
–
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
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