參數(shù)資料
型號(hào)： ICS1892
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 86/148頁
文件大?。?/td> 816K
代理商： ICS1892
ICS1892, Rev. D, 2/26/01
February 26, 2001
86
Chapter 8
Management Register Set
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.11
Register 16: Extended Control Register
Table 8-16
lists the bits for the Extended Control Register, which the ICS1892 provides to allow an STA to
customize the operations of the device.
Note:
1.
2.
For an explanation of acronyms used in
Table 8-16
, see
Chapter 1, “Abbreviations and Acronyms”
.
During any write operation to any bit in this register, the STA must write the default value to all
Reserved bits.
The default is the state of this pin at reset.
Table 8-16.
Extended Control Register (register 16 [0x10])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
16.15
Command Override Write
enable
Disabled
Enabled
RW
SC
0
–
16.14
ICS reserved
Read unspecified
Read unspecified
RW/0
–
0
16.13
ICS reserved
Read unspecified
Read unspecified
RW/0
–
0
16.12
ICS reserved
Read unspecified
Read unspecified
RW/0
–
0
16.11
ICS reserved
Read unspecified
Read unspecified
RW/0
–
0
–
16.10
PHY Address Bit 4
For a detailed explanation of this bit’s operation,
see
Section 6.9, “Status Interface”
.
RO
–
P4RD
16.9
PHY Address Bit 3
For a detailed explanation of this bit’s operation,
see
Section 6.9, “Status Interface”
.
RO
–
P3TD
16.8
PHY Address Bit 2
For a detailed explanation of this bit’s operation,
see
Section 6.9, “Status Interface”
.
RO
–
P2LI
16.7
PHY Address Bit 1
For a detailed explanation of this bit’s operation,
see
Section 6.9, “Status Interface”
.
RO
–
P1CL
–
16.6
PHY Address Bit 0
For a detailed explanation of this bit’s operation,
see
Section 6.9, “Status Interface”
.
RO
–
P0AC
16.5
Stream Cipher Test Mode
Normal operation
Test mode
RW
–
0
16.4
ICS reserved
Read unspecified
Read unspecified
RW/0
–
–
16.3
NRZ/NRZI encoding
NRZ encoding
NRZI encoding
RW
–
1
8
16.2
Transmit invalid codes
Disabled
Enabled
RW
–
0
16.1
ICS reserved
Read unspecified
Read unspecified
RW/0
–
0
16.0
Stream Cipher disable
Stream Cipher enabled Stream Cipher disabled
RW
–
0
相關(guān)PDF資料
PDF描述
ICS1892Y 10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-10 10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-14 10Base-T/100Base-TX Integrated PHYceiver
ICS1893AF 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
ICS1893Y-10 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1892Y 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-10 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-14 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1893 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893_09 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
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