參數(shù)資料
型號： ICS1892
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 34/148頁
文件大?。?/td> 816K
代理商： ICS1892
ICS1892, Rev. D, 2/26/01
February 26, 2001
34
Chapter 7
Functional Blocks
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
7.1
Functional Block: Media Independent Interface
All ICS1892 MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the
ICS1892 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz (for
10Base-T operations).
The Media Independent Interface (MII) consists of two primary components:
1.
An interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1892). This
MAC-PHY part of the MII consists of three subcomponents:
a. A synchronous
Transmit interface that includes the following signals:
(1) A data nibble, TXD[3:0]
(2) An error indicator, TXER
(3) A delimiter, TXEN
(4) A clock, TXCLK
b. A synchronous Receive interface that includes the followings signals:
(1) A data nibble, RXD[3:0]
(2) An error indicator, RXER
(3) A delimiter, RXDV
(4) A clock, RXCLK
c. A Media Status or Control interface that consists of a Carrier Sense signal (CRS) and a Collision
Detection signal (COL).
An interface between the PHY (the ICS1892) and an STA (Station Management entity). The STA-PHY
part of the MII is a two-wire, Serial Management Interface that consists of the following:
a. A clock (MDC)
b. A synchronous, bi-directional data signal (MDIO) that provides an STA with access to the ICS1892
Management Register set
2.
The ICS1892 Management Register set (discussed in
Chapter 8, “Management Register Set”
) consists of
the following:
Basic Management registers.
As defined in the ISO/IEC 8802-3 standard, these registers include the following:
– Control Register (register 0), which handles basic device configuration
– Status Register (register 1), which reports basic device capabilities and status
Extended Management registers.
As defined in the ISO/IEC 8802-3 standard, the ICS1892 supports Extended registers that provide
access to the Organizationally Unique Identifier and all auto-negotiation functionality.
ICS (Vendor-Specific) Management registers.
The ICS1892 provides vendor-specific registers for enhanced PHY operations. Among these is the
QuickPoll Detailed Status Register that provides a comprehensive and consolidated set of real-time PHY
information. Reading the QuickPoll register enables the MAC to obtain comprehensive status data with
a single register access.
相關(guān)PDF資料
PDF描述
ICS1892Y 10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-10 10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-14 10Base-T/100Base-TX Integrated PHYceiver
ICS1893AF 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
ICS1893Y-10 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1892Y 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-10 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-14 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1893 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893_09 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
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