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| 型號(hào)： | ICS1892 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁(yè)數(shù)： | 13/148頁(yè) |
| 文件大小： | 816K |
| 代理商： | ICS1892 |
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Chapter 3
ICS1892 Enhanced Features
ICS1892, Rev. D, 2/26/01
February 26, 2001
13
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
Chapter 3
ICS1892 Enhanced Features
The ICS1892 is an enhanced version of the ICS 1890. In contrast to the ICS 1890, the ICS1892 offers
significant improvements in both performance and features while maintaining backward compatibility. The
specific differences between these devices are listed below.
1.
The ICS1892 employs an advanced digital signal processing (DSP) architecture that improves the
100Base-TX Receiver performance beyond that of any other PHY in the market. Specifically:
a. The ICS1892 DSP-based, adaptive equalization process allows the ICS1892 to accommodate a
maximum cable attenuation/insertion loss of 29 dB, which is nearly equivalent to the attenuation
loss of
a 150-meter Category 5 cable.
b. The ICS1892 DSP-based, baseline-wander correction process virtually eliminates killer packets.
The analog 10Base-T Receive Phase-Locked Loop (PLL) of the ICS 1890 is replaced with a digital PLL
in the ICS1892, thereby resulting in lower jitter and improved stability.
The ICS 1890 Frequency-Locked Loop (FLL) that is part of the 100Base-TX Clock and Data Recovery
circuitry is replaced with a digital FLL in the ICS1892, also resulting in lower jitter and improved stability.
The ICS1892 transmit circuits are improved in contrast to the ICS 1890, resulting in a decrease in the
magnitude of the 10Base-T harmonic content generated during transmission. (See ISO/IEC 8802-3:
1993 clause 8.3.1.3.)
The ICS1892 supports the Auto-Negotiation Next Page functions described in IEEE Std 802.3u-1995
clause 28.2.3.4.
The ICS1892 supports Management Frame (MF) Preamble Suppression.
The ICS1892 provides the Remote Jabber capability.
The ICS1892 has an improved version of the ICS 1890 10Base-T Squelch operation.
The ICS1892 “seeds” (that is, initializes) the Transmit Stream Cipher Shift register by using the
ICS1892 PHY address from
Table 8-16
, which minimizes crosstalk and noise in repeater applications.
10. The ICS1892 offers an automatic 10Base-T power-down mode.
11. The enhanced features of the ICS1892 required some modifications to the ICS 1890 Management
Registers. However, the ICS1892 Management Registers are backward-compatible with the ICS 1890
Management Registers.
Table 3-1
summarizes the differences between the ICS 1890 and the ICS1892
Management Registers.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
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