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| 型號： | ISP1362EE,551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64 |
| 文件頁數(shù)： | 103/152頁 |
| 文件大?。?/td> | 677K |
| 代理商： | ISP1362EE,551 |
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ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
54 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
When reset by hardware or by the USB bus occurs, the Peripheral Controller disables all
endpoints and clears all ECRs, except the control endpoint that is xed and always
enabled.
An endpoint initialization can be done at any time. It is, however, valid only after
enumeration.
12.3.5 Endpoint I/O mode access
When an endpoint event occurs (a packet is transmitted or received), the associated
endpoint interrupt bits (EPn) of the DcInterrupt register (IR) are set by the SIE. The
rmware then responds to the interrupt and selects the endpoint for processing.
The endpoint interrupt bit is cleared by reading the DcEndpointStatus register (ESR). The
ESR also contains information on the status of the endpoint buffer.
For an OUT (= receive) endpoint, the packet length and packet data can be read from the
Peripheral Controller by using the Read Buffer command. When the whole packet has
been read, rmware sends a Clear Buffer command to enable the reception of new
packets.
For an IN (= transmit) endpoint, the packet length and data to be sent can be written to the
Peripheral Controller by using the Write Buffer command. When the whole packet has
been written to the buffer, rmware sends a Validate Buffer command to enable data
transmission to the host.
12.3.6 Special actions on control endpoints
Control endpoints require special rmware actions. The arrival of a set-up packet ushes
the IN buffer and disables the Validate Buffer and Clear Buffer commands for the control
IN and OUT endpoints. The microprocessor must re-enable these commands by sending
an acknowledge set-up command to both the control endpoints.
This ensures that the last set-up packet stays in the buffer and that no packets can be sent
back to the host, until the microprocessor has explicitly acknowledged that it has received
the set-up packet.
12.4 Peripheral Controller DMA transfer
Direct Memory Access (DMA) is a method to transfer data from one location to another in
a computer system, without the intervention of the CPU. Many different implementations
of DMA exist. The Peripheral Controller supports 8237 compatible mode.
8237 compatible mode: Based on the DMA subsystem of the IBM personal computers
(PC, AT and all its successors and clones). This architecture uses the Intel 8237 DMA
controller and has separate address spaces for memory and I/O.
The following features are supported:
Single-cycle or burst transfers (up to 16 bytes per cycle)
Programmable transfer direction (read or write)
Multiple End-Of-Transfer (EOT) sources: internal conditions, short or empty packet
Programmable signal levels on pins DREQ2 and DACK2
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1362EE-S | 功能描述:IC USB CTRL SNGL CHIP 64TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1362EE-T | 功能描述:USB 接口集成電路 USB OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1362EEUM | 功能描述:IC USB OTG CONTROLLER 64-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1362PCI/DOSOTG | 制造商:NXP Semiconductors 功能描述: |
| ISP1501 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hi-Speed Universal Serial Bus peripheral transceiver |
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