參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 22/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
118 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoints 1 to 14)
Transaction — none (code only)
15.2.6 DcEndpointStatusImage register (D0h to DFh)
This command is used to check the status of the selected endpoint buffer memory, without
clearing any status or interrupt bits. The command accesses the DcEndpointStatusImage
register, which contains a copy of the DcEndpointStatus register. The bit allocation of the
DcEndpointStatusImage register is shown in Table 127.
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoints 1 to 14)
Transaction — write or read 1 byte (code or data)
15.2.7 Acknowledge set up (F4h)
This command acknowledges to the host that a set-up packet is received. The arrival of a
set-up packet disables the Validate Buffer and Clear Buffer commands for the control IN
and OUT endpoints. The microprocessor must re-enable these commands by sending an
acknowledge set-up command, see Section 12.3.6.
Code (Hex): F4 — acknowledge set up
Transaction — none (code only)
Table 127. DcEndpointStatusImage register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVER
WRITE
SETUPT
CPUBUF
reserved
Reset
0000000
-
Access
RRRRRRR
-
Table 128. DcEndpointStatusImage register: bit description
Bit
Symbol
Description
7
EPSTAL
This bit indicates whether the endpoint is stalled or not (1 = stalled; 0 =
not stalled).
6
EPFULL1
Logic 1 indicates that the secondary endpoint buffer is full.
5
EPFULL0
Logic 1 indicates that the primary endpoint buffer is full.
4
DATA_PID
This bit indicates data PID of the next packet (0 = DATA0 PID; 1 =
DATA1 PID).
3
OVERWRITE
This bit is set by hardware. Logic 1 indicates that a new set-up packet
has overwritten the previous set-up information, before it was
acknowledged or before the endpoint was stalled. Once writing of the
set-up data is completed, a read back of this register clears this bit.
Firmware must check this bit before sending an acknowledge set-up
command or stalling the endpoint. On reading logic 1, rmware must
stop ongoing set-up actions and wait for a new set-up packet.
2
SETUPT
Logic 1 indicates that the buffer contains a set-up packet.
1
CPUBUF
This bit indicates which buffer is currently selected for CPU access (0 =
primary buffer; 1 = secondary buffer).
0
-
reserved
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