參數(shù)資料
型號(hào): ISP1362EE,551
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù): 129/152頁
文件大?。?/td> 677K
代理商: ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
78 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
Code (Hex): 8E — write
14.2.3 HcFmNumber register (R/W: 0Fh/8Fh)
The HcFmNumber register is a 16-bit counter, and the bit allocation is given in Table 51.It
provides a timing reference for events happening in the Host Controller and the HCD. The
HCD may use the 16-bit value specied in this register and generate a 32-bit frame
number, without requiring frequent access to the register.
Code (Hex): 0F — read
Code (Hex): 8F — write
Table 49.
HcFmRemaining register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
FRT
reserved
Reset
0
-------
Access
R/W
-------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
--------
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
FR[13:8]
Reset
-
000000
Access
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FR[7:0]
Reset
00000000
Access
R/W
Table 50.
HcFmRemaining register: bit description
Bit
Symbol
Description
31
FRT
FrameRemainingToggle: This bit is loaded from the FrameIntervalToggle
(FIT) eld of HcFmInterval whenever FrameRemaining (FR) reaches 0. This
bit is used by the HCD for synchronization between FrameInterval (FI) and
FrameRemaining (FR).
30 to 14 -
reserved
13 to 0
FR[13:0] FrameRemaining: This counter is decremented at each bit time. When it
reaches zero, it is reset by loading the FrameInterval (FI) value specied in
HcFmInterval at the next bit time boundary. When entering the
USBOperational state, the Host Controller reloads it with the content of the
FrameInterval (FI) part of the HcFmInterval register and uses the updated
value from the next SOF.
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