參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 94/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
46 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
11.6 Features of the interrupt transfer
An interrupt transaction is periodically sent out, according to the ‘interrupt polling rate’
as dened in the PTD.
An interrupt transaction causes an interrupt to the CPU only if the transaction is
ACK-ed or has error conditions, such as STALL or no respond. An ACK condition
occurs if data is received on the IN token or data is sent out on the OUT token.
An interrupt is activated only once every ms as long as there is ACK for different
interrupt transactions in the interrupt transfer buffer.
Each interrupt transfer (PTD) placed in the INTL buffer can automatically hold or send
data for more than 1 ms. This can be done using the parameters in the PTD.
11.7 Features of the Isochronous (ISO) transfer
Supports multi-buffering by using the ISTL0 or ISTL1 toggling mechanism.
The CPU can decide (in ms) how fast it can serve the ISP1362. This gives the CPU
the exibility to decide how much time it takes to read and ll in the ISO data.
The ISTL buffer can be updated on-the-y by using the direct addressing memory
architecture.
11.8 Overcurrent protection circuit
The ISP1362 has a built-in overcurrent protection circuitry. You can enable or disable this
feature by setting or resetting AnalogOCEnable (bit 10) of the HcHardwareConguration
register. If this feature is disabled, it is assumed that there is an external overcurrent
protection circuitry.
11.8.1 Using internal overcurrent detection circuit
An application using the internal overcurrent detection circuit and internal 15 k
pull-down
resistors is shown in Figure 23, where DMn denotes either OTG_DM1 or H_DM2, while
DPn denotes either OTG_DP1 or H_DP2. In this example, the HCD must set both
AnalogOCEnable and ConnectPullDown_DS1 (bit 10 and bit 12 of the
HcHardwareConguration register, respectively) to logic 1.
When H_OCn detects an overcurrent status on a downstream port, H_PSWn will output
HIGH to turn off the 5 V power supply to downstream port VBUS. When there is no such
detection, H_PSWn will output LOW to turn on the 5 V power supply to downstream port
VBUS.
Table 13.
Interrupt polling
N bits [7:5]
StartingFrame N[4:0]
Interrupt polling interval (2N) in ms
0
frame 0 to 31
1
frame 0 to 31
2
frame 0 to 31
4
3
frame 0 to 31
8
4
frame 0 to 31
16
5
frame 0 to 31
32
6
frame 0 to 31
64
7
frame 0 to 31
128
相關(guān)PDF資料
PDF描述
ISP1520BD,557 UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
ISP1520BD,557 UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
ISP1561BM,557 UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
ISP1561BM,557 UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
ISP1563BM UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1362EE-S 功能描述:IC USB CTRL SNGL CHIP 64TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1362EE-T 功能描述:USB 接口集成電路 USB OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362EEUM 功能描述:IC USB OTG CONTROLLER 64-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1362PCI/DOSOTG 制造商:NXP Semiconductors 功能描述:
ISP1501 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hi-Speed Universal Serial Bus peripheral transceiver
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*