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| 型號(hào)： | ISP1362EE,551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64 |
| 文件頁(yè)數(shù)： | 35/152頁(yè) |
| 文件大?。?/td> | 677K |
| 代理商： | ISP1362EE,551 |
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ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
13 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
7.9 GoodLink
Indication of a good USB connection is provided through the GoodLink technology
(open-drain, maximum current: 4 mA). During enumeration, LED indicators momentarily
blink on corresponding to the enumeration trafc of the ISP1362 ports. The LED also
blinks on whenever there is valid trafc to the USB ports. In ‘suspend’ mode, the LED is
off.
This feature of GoodLink provides a user-friendly indication on the status of the USB
trafc between the host and the hub, as well as the connected devices. It is a useful
diagnostics tool to isolate faulty equipment, and helps to reduce eld support and hotline
costs.
7.10 Charge pump
The charge pump generates a 5 V supply from 3.3 V to drive VBUS when the ISP1362 is
an A-device in OTG mode. For details, see Section 10.6.
8.
Host and device bus interface
The interface between the external microprocessor and the ISP1362 Host Controller (HC)
and Peripheral Controller is separately handled by the individual bus interface circuitry.
The host or device automultiplex selects the path for the host access or the device access.
This selection is determined by the A1 address line. For any access to the Host Controller
or Peripheral Controller registers, the command phase and the data phase are needed,
which is determined by the A0 address line.
All the functionality of the ISP1362 can be accessed using a group of registers and two
buffer memory areas (one for the Host Controller and the other for the Peripheral
Controller). Registers can be accessed using Programmed I/O (PIO) mode. The buffer
memory can be accessed using both PIO and Direct Memory Access (DMA) modes.
When CS is LOW (active), address pin A1 has priority over DREQ and DACK. Therefore,
as long as the CS pin is held LOW, the ISP1362 bus interface does not respond to any
DACK signals. When CS is HIGH (inactive), the bus interface will respond to DREQn and
DACKn. Address pin A1 will be ignored when CS is inactive.
An active DACKn signal when DREQn is inactive will be ignored. If DREQ1, DACK1,
DREQ2 and DACK2 are active, the bus interface will be switched off to avoid potential
data corruption.
Table 3 provides the bus access priority for the ISP1362.
[1]
Only to enable and disable the bus. Depends only on the DACK signal.
Table 3.
Bus access priority table for the ISP1362
Priority
CS
A1
DACK1
DACK2
DREQ1
DREQ2
Host Controller and Peripheral Controller active
1
L
X
Host Controller
2
L
H
X
XXXPeripheral Controller
3
H
X
L
X
H
L
Host Controller[1]
4
H
X
L
H
Peripheral Controller[1]
5
H
X
H
no driving
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| ISP1362EE-S | 功能描述:IC USB CTRL SNGL CHIP 64TFBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱(chēng):Q6396337A |
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| ISP1362EEUM | 功能描述:IC USB OTG CONTROLLER 64-TFBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱(chēng):Q6396337A |
| ISP1362PCI/DOSOTG | 制造商:NXP Semiconductors 功能描述: |
| ISP1501 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Hi-Speed Universal Serial Bus peripheral transceiver |
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