參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 132/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
80 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
14.3 HC root hub registers
All registers included in this partition are dedicated to the USB root hub, which is an
integral part of the Host Controller although it is functionally a separate entity. The HCD
emulates USB Driver (USBD) accesses to the root hub by using a register interface. The
HCD maintains many USB-dened hub features that are not required to be supported in
hardware. For example, the hub’s device, conguration, interface and endpoint descriptors
are maintained only in the HCD, as well as some static elds of the class descriptor. The
HCD also maintains and decodes the address of the root hub device and other trivial
operations that are better suited to software than to hardware.
Root hub registers are developed to maintain the similarity of bit organization and
operation to typical hubs found in the system.
Four registers are dened as follows:
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
HcRhPortStatus[1:NDP]
Each register is read and written as a double word. These registers are only written during
initialization to correspond with the system implementation. The HcRhDescriptorA and
HcRhDescriptorB registers can be read or written, regardless of the USB states of the
Host Controller. You can write to HcRhStatus and HcRhPortStatus only when the Host
Controller is in the USBOperational state.
14.3.1 HcRhDescriptorA register (R/W: 12h/92h)
The HcRhDescriptorA register is the rst of two registers describing the characteristics of
the root hub. The bit allocation is given in Table 55.
Code (Hex): 12 — read
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
LST[10:8]
Reset
-----
1
0
Access
-----
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
LST[7:0]
Reset
00101000
Access
R/W
Table 54.
HcLSThreshold register: bit description
Bit
Symbol
Description
31 to 11
-
reserved
10 to 0
LST[10:0]
LSThreshold: Contains a value that is compared to the FrameRemaining
(FR) eld before a low-speed transaction is initiated. The transaction is
started only if FrameRemaining (FR)
≥ this eld. The value is calculated by
the HCD. The HCD must consider transmission and set-up overhead, while
calculating this value.
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