參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 137/152頁
文件大小： 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
85 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
PRSC
OCIC
PSSC
PESC
CSC
Reset
-
00000
Access
-
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
LSDA
PPS
Reset
------
0
Access
------
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
PRS
POCI
PSS
PES
CCS
Reset
-
00000
Access
-
R/W
Table 62.
HcRhPortStatus[1:2] register: bit description
Bit
Symbol
Description
31 to 21
-
reserved
20
PRSC
PortResetStatusChange: This bit is set at the end of the 10 ms port
reset signal. The HCD writes logic 1 to clear this bit. Writing logic 0
has no effect.
0 — port reset is not complete
1 — port reset is complete
19
OCIC
PortOverCurrentIndicatorChange: This bit is valid only if overcurrent
conditions are reported on a per-port basis. This bit is set when the
root hub changes the PortOverCurrentIndicator (POCI) bit. The HCD
writes logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no change in PortOverCurrentIndicator (POCI)
1 — PortOverCurrentIndicator (POCI) has changed
18
PSSC
PortSuspendStatusChange: This bit is set when the full resume
sequence is complete. This sequence includes the 20 ms resume
pulse, LS EOP and 3 ms re-synchronization delay. The HCD writes
logic 1 to clear this bit. Writing logic 0 has no effect. This bit is also
cleared when PortResetStatusChange is set.
0 — resume is not completed
1 — resume is completed
17
PESC
PortEnableStatusChange: This bit is set when hardware events
cause the PortEnableStatus (PES) bit to be cleared. Changes from the
HCD writes do not set this bit. The HCD writes logic 1 to clear this bit.
Writing logic 0 has no effect.
0 — no change in PortEnableStatus (PES)
1 — change in PortEnableStatus (PES)
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