參數資料
型號: ISP1362EE,551
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數: 77/152頁
文件大?。?/td> 677K
代理商: ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
30 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
9.
Power-On Reset (POR)
When VCC is directly connected to the RESET pin, the internal POR pulse width (tPORP)
will typically be 800 ns. The pulse is started when VCC rises above Vtrip (2.03 V).
To give a better view of the functionality, Figure 15 shows a possible curve of VCC with
dips at t2 to t3 and t4 to t5. If the dip at t4 to t5 is too short (that is, < 11
s), the internal
POR pulse will not react and will remain LOW. The internal POR starts with a HIGH at t0.
At t1, the detector will see the passing of the trip level and a delay element will add
another tPORP before it drops to LOW.
The internal POR pulse will be generated whenever VCC drops below Vtrip for more than
11
s.
The RESET pin can be either connected to VCC (using the internal POR circuit) or
externally controlled (by the micro, ASIC, and so on). Figure 16 shows the availability of
the clock with respect to the external reset pulse.
(1) PORP = Power-On Reset Pulse.
Fig 15. Internal power-on reset timing
Stable external clock is available at A.
Fig 16. Clock with respect to the external power-on reset
004aaa482
VCC
t0
t1
t2
t3
t4
t5
Vtrip
tPORP
PORP(1)
tPORP
RESET
EXTERNAL CLOCK
A
004aaa484
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