參數(shù)資料
型號(hào)： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 128/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
77 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
adjustments on FrameInterval by writing a new value over the present one at each SOF.
This provides the programmability necessary for the Host Controller to synchronize with
an external clocking resource and to adjust any unknown local clock offset.
Code (Hex): 0D — read
Code (Hex): 8D — write
14.2.2 HcFmRemaining register (R/W: 0Eh/8Eh)
The HcFmRemaining register is a 14-bit down counter, showing the bit time remaining in
the current frame. The bit allocation is given in Table 49.
Code (Hex): 0E — read
Table 47.
HcFmInterval register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
FIT
FSMPS[14:8]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
FSMPS[7:0]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
FI[13:8]
Reset
-
101110
Access
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FI[7:0]
Reset
11011111
Access
R/W
Table 48.
HcFmInterval register: bit description
Bit
Symbol
Description
31
FIT
FrameIntervalToggle: The HCD toggles this bit whenever it loads a
new value to FrameInterval.
30 to 16
FSMPS
[14:0]
FSLargestDataPacket: Species a value that is loaded into the
largest data packet counter at the beginning of each frame. The
counter value represents the largest amount of data in bits that can be
sent or received by the Host Controller in a single transaction at any
given time, without causing a scheduling overrun. The eld value is
calculated by the HCD.
15 to 14
-
reserved
13 to 0
FI[13:0]
FrameInterval: Species the interval between two consecutive SOFs
in bit times. The nominal value is set to 11999. The HCD must store
the current value of this eld before resetting the Host Controller.
Setting the HostControllerReset (HCR) eld of the HcCommandStatus
register causes the Host Controller to reset this eld to its nominal
value. The HCD may choose to restore the stored value on completing
the reset sequence.
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