參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 122/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
71 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
--------
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
RWE
RWC
reserved
Reset
-----
0
-
Access
-----
R/W
-
Bit
7
6
5
4
3
2
1
0
Symbol
HCFS[1:0]
reserved
Reset
0
------
Access
R/W
------
Table 38.
HcControl register: bit description
Bit
Symbol
Description
31 to 11
-
reserved
10
RWE
RemoteWakeupEnable: This bit is used by the HCD to enable or
disable the remote wake-up feature on detecting upstream resume
signaling. When this bit and the ResumeDetected (RD) bit in
HcInterruptStatus are set, a remote wake-up is signaled to the host
system. Setting this bit has no impact on the generation of hardware
interrupt.
9RWC
RemoteWakeupConnected: This bit indicates whether the Host
Controller supports remote wake-up signaling. If remote wake-up is
supported and used by the system, it is the responsibility of the
system rmware to set this bit during POST. The Host Controller
clears the bit on a hardware reset but does not alter it on a software
reset. Remote wake-up signaling of the host system is
host-bus-specic and is not described in this specication.
8
-
reserved
7 to 6
HCFS[1:0]
HostControllerFunctionalState for USB
00 — USBReset
01 — USBResume
10 — USBOperational
11 — USBSuspend
A transition to USBOperational from another state causes
Start-Of-Frame (SOF) generation to begin 1 ms later. The HCD may
determine whether the Host Controller has begun sending SOFs by
reading the StartofFrame (SF) eld of HcInterruptStatus.
This eld may be changed by the Host Controller only when it is in the
USBSuspend state. The Host Controller may move from the
USBSuspend state to the USBResume state after detecting the
resume signaling from a downstream port.
The Host Controller enters USBReset either by a software reset or by
a hardware reset. The latter also resets the root hub and asserts
subsequent reset signaling to downstream ports.
5 to 0
-
reserved
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