參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 20/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
116 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
Remark: There is no protection against writing or reading past a buffer’s boundary,
against writing into an OUT buffer or reading from an IN buffer. Any of these actions can
cause an incorrect operation. Data residing in an OUT buffer is only meaningful after a
successful transaction. Exception: during the DMA access of a double-buffered endpoint,
the buffer pointer automatically points to the secondary buffer after reaching the end of the
primary buffer.
15.2.2 Read endpoint status (R: 50h to 5Fh)
This command is used to read the status of an endpoint buffer memory. The command
accesses the DcEndpointStatus register, the bit allocation of which is shown in Table 125.
Reading the DcEndpointStatus register will clear the interrupt bit set for the corresponding
endpoint in the DcInterrupt register (see Table 141).
All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by the
Stall or Unstall commands and by the reception of a set-up token (see Section 15.2.3).
Code (Hex): 50 to 5F — read (control OUT, control IN, endpoints 1 to 14)
Transaction — read 1 byte (code only)
Table 124. Example of endpoint buffer memory access
A0
Phase
Bus lines
Word #
Description
HIGH
command
D[7:0]
-
command code (00h to 1Fh)
D[15:8]
-
ignored
LOW
data
D[15:0]
0
packet length
LOW
data
D[15:0]
1
data word 1 (data byte 2, data byte 1)
LOW
data
D[15:0]
2
data word 2 (data byte 4, data byte 3)
…
………
…
Table 125. DcEndpointStatus register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVER
WRITE
SETUPT
CPUBUF
reserved
Reset
0000000
-
Access
RRRRRRR
-
Table 126. DcEndpointStatus register: bit description
Bit
Symbol
Description
7
EPSTAL
This bit indicates whether the endpoint is stalled or not (1 = stalled; 0 =
not stalled).
Set to logic 1 by a stall endpoint command, cleared to logic 0 by an
Unstall Endpoint command. The endpoint is automatically unstalled on
receiving a set-up token.
6
EPFULL1
Logic 1 indicates that the secondary endpoint buffer is full.
5
EPFULL0
Logic 1 indicates that the primary endpoint buffer is full.
4
DATA_PID
This bit indicates data PID of the next packet (0 = DATA PID; 1 = DATA1
PID).
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