參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 135/152頁
文件大小： 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
83 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
14.3.3 HcRhStatus register (R/W: 14h/94h)
The HcRhStatus register is divided into two parts. The lower word of a double-word
represents the hub status eld and the upper word represents the hub status change eld.
Reserved bits should always be written as logic 0. See Table 59 for bit allocation of the
register.
Code (Hex): 14 — read
Code (Hex): 94 — write
Table 58.
HcRhDescriptorB register: bit description
Bit
Symbol
Description
31 to 19
-
reserved
18 to 16
PPCM[2:0] PortPowerControlMask: Each bit indicates whether a port is affected by a
global power control command when PowerSwitchingMode is set. When
set, the power state of the port is only affected by per-port power control
(Set/ClearPortPower). When cleared, the port is controlled by the global
power switch (Set/ClearGlobalPower). If the device is congured to global
switching mode (PowerSwitchingMode = 0), this eld is not valid.
Bit 2 — ganged-power mask on port 2
Bit 1 — ganged-power mask on port 1
Bit 0 — reserved
15 to 3
-
reserved
2 to 0
DR[2:0]
DeviceRemovable: Each bit is dedicated to a port of the root hub. When
cleared, the attached device is removable. When set, the attached device
is not removable.
Bit 2 — device attached to port 2
Bit 1 — device attached to port 1
Bit 0 — reserved
Table 59.
HcRhStatus register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
CRWE
reserved
Reset
0
-------
Access
W
-------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
CCIC
LPSC
Reset
------
0
Access
------
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
DRWE
reserved
Reset
0
-------
Access
R/W
-------
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
OCI
LPS
Reset
------
0
Access
------
R
R/W
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