參數(shù)資料
型號: ISP1362EE,551
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù): 8/152頁
文件大?。?/td> 677K
代理商: ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
105 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
14.9.8 HcATLPTDDoneThresholdCount register (R/W: 51h/D1h)
This register species the number of ATL PTDs to be done to trigger an ATL interrupt. If
set to 08h, the Host Controller will trigger the ATL interrupt (in the Hc
PInterrupt register)
once every eight ATL PTDs are done. Table 104 shows the bit allocation of the register.
Remark: Do not write 0000h to this register.
Code (Hex): 51 — read
Code (Hex): D1 — write
14.9.9 HcATLPTDDoneThresholdTimeOut register (R/W: 52h/D2h)
This is a time-out register used to generate an ATL interrupt. The value in this register
indicates the maximum allowable time in milliseconds for the Host Controller to retry a
NAK transaction. This register can be used in combination with
HcATLPTDDoneThresholdCount. Table 106 shows the bit allocation of the
HcATLPTDDoneThresholdCount register.
Remark: If the time-out indication is not required by software, or there is no active PTD in
the ATL buffer, write 0000h to this register.
Code (Hex): 52 — read
Code (Hex): D2 — write
Table 104. HcATLPTDDoneThresholdCount register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
--------
Access
--------
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
PTDDoneCount[4:0]
Reset
-
00001
Access
-
R/W
Table 105. HcATLPTDDoneThresholdCount register: bit description
Bit
Symbol
Description
15 to 5
-
reserved
4 to 0
PTDDoneCount
[4:0]
Number of PTDs to be processed by the Host Controller to generate an
ATL interrupt.
Table 106. HcATLPTDDoneThresholdTimeOut register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
--------
Access
--------
Bit
7
6
5
4
3
2
1
0
Symbol
PTDDoneTimeOut[7:0]
Reset
00000001
Access
R/W
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