參數(shù)資料
型號(hào)： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 104/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
55 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
12.4.1 Selecting an endpoint for the DMA transfer
The target endpoint for DMA access is selected using bits EPDIX[3:0] of the
DcDMAConguration register, as shown in Table 17. The transfer direction (read or write)
is automatically set by the EPDIR bit in the associated ECR, to match the selected
endpoint type (OUT endpoint: read; IN endpoint: write).
Automatically asserting input DACK2 selects the endpoint specied in the
DcDMAConguration register, regardless of the current endpoint used for I/O mode
access.
12.4.2 8237 compatible mode
This mode is selected by clearing the DAKOLY bit of the DcHardwareConguration
register (see Table 115). The pin functions for this mode are shown in Table 18.
The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA controller.
It operates as a ‘y-by’ DMA controller. Data is not stored in the DMA controller, but it is
transferred between an I/O port and a memory address. A typical example of the
Peripheral Controller in 8237 compatible DMA mode is given in Figure 26.
Table 17.
Endpoint selection for the DMA transfer
Endpoint
identier
EPIDX[3:0]
Transfer direction
EPDIR = 0
EPDIR = 1
1
0010
OUT: read
IN: write
2
0011
OUT: read
IN: write
3
0100
OUT: read
IN: write
4
0101
OUT: read
IN: write
5
0110
OUT: read
IN: write
6
0111
OUT: read
IN: write
7
1000
OUT: read
IN: write
8
1001
OUT: read
IN: write
9
1010
OUT: read
IN: write
10
1011
OUT: read
IN: write
11
1100
OUT: read
IN: write
12
1101
OUT: read
IN: write
13
1110
OUT: read
IN: write
14
1111
OUT: read
IN: write
Table 18.
8237 compatible mode: pin functions
Symbol Description
I/O
Function
DREQ2
DMA request of Peripheral
Controller
O
Peripheral Controller requests a DMA
transfer
DACK2
DMA acknowledge of Peripheral
Controller
I
DMA controller conrms the transfer
EOT
end of transfer
I
DMA controller terminates the transfer
RD
read strobe
I
instructs the Peripheral Controller to put
data on the bus
WR
write strobe
I
instructs the Peripheral Controller to get
data from the bus
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