參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 46/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
14 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
8.1 Memory organization
The buffer memory in the Host Controller uses a multicongurable direct addressing
architecture. The 4096 bytes Host Controller buffer memory is shared by the ISTL0,
ISTL1, INTL and ATL buffers. ISTL0 and ISTL1 are used for isochronous trafc (double
buffer), INTL is used for interrupt trafc, and ATL is used for control and bulk trafc.
The allocation of the buffer memory follows the sequence ISTL0, ISTL1, INTL, ATL and
unused memory. For example, consider that the buffer sizes of the ISTL, INTL and ATL
buffers are 1024 bytes, 1024 bytes and 1024 bytes, respectively. Then, ISTL0 will start
from memory location 0, ISTL1 will start from memory location 1024 (size of ISTL0), INTL
will start from memory location 2048 (size of ISTL0 + size of ISTL1) and ATL will start
from memory location 3072 (size of ISTL0 + size of ISTL1 + size of INTL).
The Host Controller Driver (HCD) has the responsibility to ensure that the sum of the four
memory buffers does not exceed the total memory size. If this condition is violated, it will
lead to data corruption. The buffer size must be a multiple of 2 bytes (one word).
The buffer memory of the Peripheral Controller follows a similar architecture. Details on
the Peripheral Controller memory area allocation can be found in Section 12.3. Note that
the Peripheral Controller buffer memory does not support direct addressing mode.
8.1.1 Memory organization for the Host Controller
The Host Controller in the ISP1362 has a total of 4096 bytes of buffer memory. This buffer
area is divided into four parts (see Table 4 and Figure 4).
The ISTL0 and ISTL1 buffers must have the same size. Memory is allocated by the Host
Controller according to the value set by the HCD in HcISTLBufferSize, HcINTLBufferSize
and HcATLBufferSize. All buffer sizes must be multiples of 2 bytes (one word).
Table 4.
Buffer memory areas and their applications
Buffer memory area
Application
ISTL0 and ISTL1
isochronous transfer (double buffering)
INTL
interrupt transfer
ATL
control and bulk transfer
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