參數(shù)資料
型號: MFRC53001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 A Reader IC
封裝: MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù): 10/115頁
文件大?。?/td> 2590K
代理商: MFRC53001T
MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
10 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
Table 6.
MFRC530 pins
ALE
A2
A1
A0
NRD
NWR
NCS
D7 to D1
D0
Figure 6
shows the microprocessor connection to the MFRC530 using SPI.
Remark:
The SPI implementation for MFRC530 conforms to the SPI standard and
ensures that the MFRC530 can only be addressed as a slave.
9.1.4.1
SPI read data
The structure shown in
Table 7
must be used to read data using SPI. It is possible to read
up to n-data bytes. The first byte sent defines both, the mode and the address.
Table 7.
Pin
MOSI
MISO
The address byte must meet the following criteria:
the Most Significant Bit (MSB) of the first byte sets the mode. To read data from the
MFRC530 the MSB is set to logic 1
bits [6:1] define the address
the Least Significant Bit (LSB) should be set to logic 0.
As shown in
Table 8
, all the bits of the last byte sent are set to logic 0.
SPI compatibility
SPI pins
NSS
SCK
LOW
MOSI
HIGH
HIGH
LOW
do not connect
MISO
Fig 6.
Connection to microprocessor: SPI
001aak610
LOW
NCS
D0
ALE
A2
SCK
A1
LOW
MOSI
NSS
A0
MISO
DEVICE
SPI read data
Byte 0
address 0
XX
Byte 1
address 1 address 2 ...
data 0
data 1
Byte 2
...
Byte n
address n
data n
1
Byte n + 1
00
data n
...
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