參數(shù)資料
型號: MFRC53001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 A Reader IC
封裝: MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù): 94/115頁
文件大小: 2590K
代理商: MFRC53001T
MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
94 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
Remark:
Figure 22
does not distinguish between the address write cycle and a data write
cycle. The timings for the address write and data write cycle are different. In EPP mode,
the address lines (A0 to A2) must be connected as described in
Section 9.1.3 on page 8
.
t
DSHDZ
data strobe HIGH to data input high
impedance time
data strobe LOW to data output
valid time
data output hold after data strobe
HIGH time
write hold after data strobe HIGH
time
data strobe LOW time
write LOW to data strobe LOW time nWrite valid to
read cycle
-
-
20
ns
t
DSLQV
nDStrb LOW
-
-
35
ns
t
DSHQX
NCS HIGH
8
-
-
ns
t
DSHWX
nWrite
8
-
-
ns
t
DSLDSH
t
WLDSL
nDStrb
65
8
-
-
-
-
ns
ns
nDStrb LOW
nDStrb LOW to
nWrite HIGH
nDStrb HIGH to
nWrite LOW
t
DSL-WAITH
data strobe LOW to WAIT HIGH
time
data strobe HIGH to WAIT LOW
time
-
-
75
ns
t
DSH-WAITL
-
-
75
ns
Fig 22. Timing diagram for common read/write strobe; EPP
Table 163. Common read/write strobe timing specification for EPP
…continued
Symbol
Parameter
Conditions
Min
Typ
Max Unit
001aaj640
nWait
t
DSL-WAITH
t
DSLDV
t
DSLQV
t
WLDSL
t
SLDSL
t
DSHSH
t
DSLDSH
D0 to D7
A0 to A7
t
DSHQX
t
DSHDZ
t
DSH-WAITL
t
DSHWX
D0 to D7
nDStrb
nAStrb
nWrite
NCS
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