參數(shù)資料
型號： MFRC53001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡
英文描述： ISO-IEC 14443 A Reader IC
封裝： MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù)： 15/115頁
文件大?。?/td> 2590K
代理商： MFRC53001T
MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
15 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
9.2.2.3
Register initialization file (read/write)
The EEPROM memory content from block address 3 to 7 can initialize register
subaddresses 10h to 2Fh when the LoadConfig command is executed (see
Section 11.4.1 on page 84
). This command requires the EEPROM starting byte address
as a two byte argument for the initialization procedure.
The byte assignment is shown in
Table 17
.
Table 17.
EEPROM byte address
EEPROM starting byte address
EEPROM + 1 starting byte address
The register initialization file is large enough to hold values for two initialization sets and
up to one block (16-byte) of user data.
Remark:
The register initialization file can be read/written by users and these bytes can
be used to store other user data.
After each power-up, the default configuration enables the MIFARE and ISO/IEC 14443 A
protocol.
9.2.3
Crypto1 keys (write only)
MIFARE security requires specific cryptographic keys to encrypt data stream
communication on the contactless interface. These keys are called Crypto1 keys.
9.2.3.1
Key format
Keys stored in the EEPROM are written in a specific format. Each key byte must be split
into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble).
Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This
format is a precondition for successful execution of the LoadKeyE2 (see
Section 11.6.1 on
page 86
) and LoadKey commands (see
Section 11.6.2 on page 86
).
29h
29h
08h
FIFOLevel
WaterLevel[5:0] FIFO buffer warning level is set to standard
configuration
TPreScaler[4:0] is set to standard configuration, timer unit restart
function is switched off
Timer is started at the end of transmission, stopped at the beginning
of reception
TReloadValue[7:0]: the timer unit preset value is set to standard
configuration
pin IRQ is set to high-impedance
-
-
2Ah
2Ah
07h
TimerClock
2Bh
2Bh
06h
TimerControl
2Ch
2Ch
0Ah
TimerReload
2Dh
2Eh
2Fh
2Dh
2Eh
2Fh
02h
00h
00h
IRQPinConfig
PreSet2E
PreSet2F
Table 16.
EEPROM
byte
address
Shipment content of StartUp configuration file
…continued
Register
address
Value
Symbol
Description
Byte assignment for register initialization at startup
Register address
10h
11h
…
2Fh
Remark
skipped
copied
…
copied
EEPROM + 31 starting byte address
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