參數(shù)資料
型號(hào)： MFRC53001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 A Reader IC
封裝： MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù)： 27/115頁
文件大小： 2590K
代理商： MFRC53001T
MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
27 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
9.7.3
Initialization phase
The initialization phase automatically follows the reset phase and takes 128 clock cycles.
During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the
register subaddresses 10h to 2Fh (see
Section 9.2.2 on page 13
).
Remark:
During the production test, the MFRC530 is initialized with default configuration
values. This reduces the microprocessor’s configuration time to a minimum.
9.7.4
Initializing the parallel interface type
A different initialization sequence is used for each microprocessor. This enables detection
of the correct microprocessor interface type and synchronization of the microprocessor’s
and the MFRC530’s start-up. See
Section 9.1.3 on page 8
for detailed information on the
different connections for each microprocessor interface type.
During StartUp phase, the command value is set to 3Fh once the oscillator attains clock
frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At
the end of the initialization phase, the MFRC530 automatically switches to idle and the
command value changes to 00h.
To ensure correct detection of the microprocessor interface, the following sequence is
executed:
the Command register is read until the 6-bit register value is 00h. On reading the 00h
value, the internal initialization phase is complete and the MFRC530 is ready to be
controlled
write 80h to the Page register to initialize the microprocessor interface
read the Command register. If it returns a value of 00h, the microprocessor interface
was successfully initialized
write 00h to the Page registers to activate linear addressing mode.
9.8 Oscillator circuit
The clock applied to the MFRC530 acts as a time basis for the synchronous system
encoder and decoder. The stability of the clock frequency is an important factor for correct
operation. To obtain highest performance, clock jitter must be as small as possible. This is
best achieved by using the internal oscillator buffer with the recommended circuitry.
Fig 10. Quartz clock connection
001aak614
13.56 MHz
15 pF
15 pF
OSCOUT
OSCIN
DEVICE
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MFRC53001T/0FE,112 功能描述:RFID應(yīng)答器 MIFARE HS READER RoHS:否 制造商:Murata 存儲(chǔ)容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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