參數(shù)資料
型號： MFRC53001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網絡
英文描述： ISO-IEC 14443 A Reader IC
封裝： MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù)： 31/115頁
文件大小： 2590K
代理商： MFRC53001T
MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
31 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
9.10 Receiver circuit
The MFRC530 uses an integrated quadrature demodulation circuit enabling it to extract
the ISO/IEC 14443 A compliant subcarrier from the 13.56 MHz ASK modulated signal
applied to pin RX.
The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a
phase-shift of 90
°
between them. Both resulting subcarrier signals are amplified, filtered
and forwarded to the correlation circuitry. The correlation results are evaluated, digitized
and then passed to the digital circuitry. Various adjustments can be made to obtain
optimum performance for all processing units.
9.10.1
Receiver circuit block diagram
Figure 11
shows the block diagram of the receiver circuit. The receiving process can be
broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal
is performed. To achieve the optimum performance, automatic Q-clock calibration is
recommended (see
Section 9.10.2.1 on page 32
).
The demodulated signal is amplified by an adjustable amplifier. A correlation circuit
calculates the degree of similarity between the expected and the received signal. The
BitPhase register enables correlation interval position alignment with the received signal’s
bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital
results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
The signal can be observed on its way through the receiver as shown in
Figure 11
. One
signal at a time can be routed to pin AUX using the TestAnaSelect register as described in
Section 15.2.2 on page 101
.
9.10.2
Receiver operation
In general, the default settings programmed in the StartUp initialization file are suitable for
use with the MFRC530 to MIFARE card data communication. However, in some
environments specific user settings will achieve better performance.
Fig 11. Receiver circuit block diagram
001aak615
ClkQDelay[4:0]
ClkQCalib
ClkQ180Deg
BitPhase[7:0]
CORRELATION
CIRCUITRY
EVALUATION
AND
DIGITIZER
CIRCUITRY
MinLevel[3:0]
CollLevel[3:0]
RxWait[7:0]
RcvClkSell
s_valid
s_data
s_coll
s_clock
Gain[1:0]
to
TestAnaOutSel
clock
I TO Q
CONVERSION
I-clock
Q-clock
13.56 MHz
DEMODULATOR
RX
VCorrDI
VCorrNI
VCorrDQ
VCorrNQ
VEvalR
VEvalL
VRxFollQ
VRxFollI
VRxAmpI
VRxAmpQ
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MFRC53001T/0FE,112 功能描述:RFID應答器 MIFARE HS READER RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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