參數(shù)資料
型號: MFRC53001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 A Reader IC
封裝: MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù): 92/115頁
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代理商: MFRC53001T
MFRC530_33
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NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
92 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
Remark:
The signal ALE is not relevant for separate address/data bus and the
multiplexed addresses on the data bus do not care. The multiplexed address and data bus
address lines (A0 to A2) must be connected as described in
Section 9.1.3 on page 8
.
13.4.2
Common read/write strobe bus timing
Table 162. Common read/write strobe timing specification
Symbol
Parameter
t
LHLL
ALE HIGH time
t
AVLL
address valid to ALE LOW time
t
LLAX
address hold after ALE LOW time
t
LLDSL
ALE LOW to data strobe LOW time
Fig 20. Separate read/write strobe timing diagram
001aaj638
t
SLRWL
t
RWHSH
t
RWHRWL
t
WHDX
t
RHDZ
t
WLQV
t
RLDV
t
AVRWL
t
WHAX
t
LLAX
t
AVLL
t
RWLRWH
t
LLRWL
t
RWHRWL
t
LHLL
A0 to A2
A0 to A2
D0 to D7
D0 to D7
NWR
NRD
NCS
ALE
A0 to A2
Multiplexed address bus
Separated address bus
Conditions
Min
20
15
8
15
Typ
-
-
-
-
Max Unit
-
-
-
-
ns
ns
ns
ns
NWR or NRD
LOW
NCS LOW to
NDS LOW
t
SLDSL
chip select LOW to data strobe
LOW time
data strobe HIGH to chip select
HIGH time
data strobe LOW to data input valid
time
data strobe HIGH to data input high
impedance time
data strobe LOW to data output
valid time
data output hold after data strobe
HIGH time
RW hold after data strobe HIGH
time
data strobe LOW time
0
-
-
ns
t
DSHSH
0
-
-
ns
t
DSLDV
-
-
65
ns
t
DSHDZ
-
-
20
ns
t
DSLQV
NDS/NCS LOW
-
-
35
ns
t
DSHQX
NDS HIGH (write
cycle hold time)
after NDS HIGH
8
-
-
ns
t
DSHRWX
8
-
-
ns
t
DSLDSH
NDS/NCS
65
-
-
ns
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