參數(shù)資料
型號: MFRC53001T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 A Reader IC
封裝: MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù): 11/115頁
文件大小: 2590K
代理商: MFRC53001T
MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
11 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
Table 8.
Address
(MOSI)
byte 0
byte 1 to byte n reserved address address address address address address reserved
byte n + 1
0
0
0
0
[1]
All reserved bits must be set to logic 0.
9.1.4.2
SPI write data
The structure shown in
Table 9
must be used to write data using SPI. It is possible to write
up to n-data bytes. The first byte sent defines both the mode and the address.
Table 9.
The address byte must meet the following criteria:
the MSB of the first byte sets the mode. To write data to the MFRC530, the MSB is set
to logic 0
bits [6:1] define the address
the LSB should be set to logic 0.
SPI write mode writes all data to the address defined in byte 0 enabling effective write
cycles to the FIFO buffer.
Table 10.
Address line
(MOSI)
byte 0
byte 1 to byte
n + 1
[1]
All reserved bits must be set to logic 0.
Remark:
The data bus pins D7 to D0 must be disconnected.
Refer to
Section 13.4.4 on page 95
for the timing specification.
SPI read address
Bit 7
(MSB)
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
[1]
address address address address address address reserved
0
0
0
0
SPI write data
Byte 0
address
XX
Byte 1
data 0
XX
Byte 2
data 1
XX
...
...
...
Byte n
data n
1
XX
Byte n + 1
data n
XX
MOSI
MISO
SPI write address
Bit 7
(MSB)
0
data
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
[1]
reserved
data
address
data
address
data
address
data
address
data
address
data
address
data
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