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參數資料
| 型號： | MFRC53001T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網絡 |
| 英文描述： | ISO-IEC 14443 A Reader IC |
| 封裝： | MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1 |
| 文件頁數： | 39/115頁 |
| 文件大?。?/td> | 2590K |
| 代理商： | MFRC53001T |
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MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
39 of 115
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
10. MFRC530 registers
10.1 Register addressing modes
Three methods can be used to operate the MFRC530:
initiating functions and controlling data by executing commands
configuring the functional operation using a set of configuration bits
monitoring the state of the MFRC530 by reading status flags
The commands, configuration bits and flags are accessed using the microprocessor
interface. The MFRC530 can internally address 64 registers using six address lines.
10.1.1
Page registers
The MFRC530 register set is segmented into eight pages contain eight registers each. A
Page register can always be addressed, irrespective of which page is currently selected.
10.1.2
Dedicated address bus
When using the MFRC530 with the dedicated address bus, the microprocessor defines
three address lines using address pins A0, A1 and A2. This enables addressing within a
page. To switch between registers in different pages a paging mechanism needs to be
used.
Table 34
shows how the register address is assembled.
Table 34.
Register bit: UsePageSelect
1
10.1.3
Multiplexed address bus
The microprocessor may define all six address lines at once using the MFRC530 with a
multiplexed address bus. In this case either the paging mechanism or linear addressing
can be used.
Table 35
shows how the register address is assembled.
Table 35.
Multiplexed
address bus
type
Paging mode
Linear
addressing
Dedicated address bus: assembling the register address
Register address
PageSelect2
PageSelect1
PageSelect0
A2
A1
A0
Multiplexed address bus: assembling the register address
UsePage
Select
Register address
1
0
PageSelect2 PageSelect1
AD5
PageSelect0
AD3
AD2
AD2
AD1 AD0
AD1 AD0
AD4
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MFRC53001T/0FE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ISO/IEC 14443 A Reader IC |
| MFRC53001T/0FE,112 | 功能描述:RFID應答器 MIFARE HS READER RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC53001T/0FE,518 | 功能描述:RFID應答器 IC READER 13.56MHZ RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC53001T/0FE112 | 制造商:NXP Semiconductors 功能描述:CNTCLESS RC 3.3V ISO14443-A/B |
| MFRC531 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Short Form Specification |
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