MOTOROLA
Chapter 21. CDR3 Flash (UC3F) EEPROM
21-19
Programming Model
15
IWS
Interlock write select — This bit determines which interlock write operation should be used during the
clear censorship operation.
IWS always comes from the UC3FCFIG, it will never use the external reset configuration word
(RSTCONF=0) or the default internal reset configuration word (RSTCONF=1 and HC=1).
0 Interlock write is a write to any UC3F array location
1 Interlock write is a write to the UC3FMCR register.
16
PRPM
Peripheral mode enable — This bit determines if the chip is in peripheral mode. A detailed description
is in
Table 6-13. The default value is no peripheral mode enabled.
17:18
SC
Single chip select — This field defines the mode of the MPC563.
00 Extended chip, 32 bits data
01 Extended chip, 16 bits data
10 Single chip and show cycles (address)
11 Single chip
19
ETRE
Exception table relocation enable — This field defines whether the Exception Table Relocation feature
in the BBC is enabled or disabled. The default state for this field is disabled. For more details, see
20
HC
Has configuration – This bit determines if the Flash Reset Configuration word is valid.
0 The Flash shadow row contains a valid Reset Configuration Word
1 The Flash shadow row does not contain a valid Reset Configuration Word
21
EN_COMP 1 Enable compression — This bit enables the operation of the MPC564 with compressed code. See
22
EXC_COMP1 Exception compression — This bit determines the operation of the MPC564 with exceptions.
0 indicates the exceptions are all non-compressed. See
Table 4-4.1 the MPC564 assumes that ALL the exception routines are in compressed code.
23
—
Reserved. This bit must be programmed low in the reset configuration word.
24:25
OERC
Other exceptions relocation control — These bits effect only if ETRE was enabled.
Relocation offset:
00 Offset 0
01 Offset 64 Kbytes
10 Offset 512 Kbytes
11 Offset to 0x003F E000
26:27
—
Reserved
28:30
ISB
Internal space base select — This field defines the initial value of the ISB field in the IMMR register. A
detailed description is in
Table 6-12. The default state is that the internal memory map is mapped to start
at address 0x0000_0000. This bit must not be high in the reset configuration word.
31
DME
Dual mapping enable — This bit determines whether Dual mapping of the internal Flash is enabled. For
a detailed description refer to
Table 10-12. The default state is that dual mapping is disabled.
0 Dual mapping disabled
1 Dual mapping enabled
1 This bit is available only on the MPC564.
Table 21-6. RCW Bit Descriptions (continued)
Bits
Name
Description