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參數(shù)資料
| 型號： | MT48LC32M4A2P-7ELIT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 14/74頁 |
| 文件大?。?/td> | 2385K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
21
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Commands
Table 7 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional truth tables appear following “Opera-
tions” on page 24; these tables provide current state/next state information.
Table 7:
Truth Table 1 – Commands and DQM Operation
CKE is HIGH for all commands shown except SELF REFRESH
Name (Function)
CS#
RAS#
CAS#
WE#
DQM
ADDR
DQ
Notes
COMMAND INHIBIT (NOP)
H
X
NO OPERATION (NOP)
L
H
X
ACTIVE (Select bank and activate row)
L
H
X
Bank/
row
X
READ (Select bank and column, and start READ
burst)
L
H
L
H
L/H8
Bank/
col
X
WRITE (Select bank and column, and start WRITE
burst)
L
H
L
L/H8
Bank/
col
Valid
BURST TERMINATE
L
H
L
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
H
L
X
Code
X
AUTO refresh or self refresh
(Enter self refresh mode)
L
H
X
LMR
L
X
Op-
code
X
Write enable/output enable
–
L
–
Active
Write inhibit/output High-Z
–
H
–
High-Z
Notes:
1. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
2. A0–A9; A11 (x4); A0–A9 (x8); or A0–A8 (x16) provide column address; A10 HIGH enables the
auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge fea-
ture; BA0, BA1 determine which bank is being read from or written to.
3. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
4. This command is AUTO REFRESH if CKE is HIGH and SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
6. A0–A11 define the op-code written to the mode register.
7. Activates or deactivates the DQ during WRITEs (0-clock delay) and READs (2-clock delay).
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM, which is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
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